參數(shù)資料
型號： EVAL-ADAU1442EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 29/93頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADAU1442
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
主要目的： 音頻，音頻處理
嵌入式： 是，DSP
已用 IC / 零件： ADAU1442
主要屬性： 單芯片多通道 28/56 位音頻 DSP
次要屬性： I²C & SPI 接口
已供物品： 電路板，線纜，說明文檔，GPIO 子板，電源
ADAU1442/ADAU1445/ADAU1446
Data Sheet
Rev. D | Page 34 of 92
Serial Clock Domains
There are 12 clock domains (pairs of LRCLKx and BCLKx pins)
available in the ADAU1442/ADAU1445/ADAU1446. Of these,
three are available exclusively to the serial data input ports, three
are available exclusively to the serial data output ports, and the
remaining six can be assigned to clock either input or output ports.
The ADAU1442 contains eight 2-channel ASRCs and the
ADAU1445 contains two 8-channel ASRCs, whereas the
ADAU1446 contains no ASRCs. However, all clock domain pins
are available on every device. In a system with no sample rate
conversion and with serial ports in slave mode, at least two
pairs of LRCLKx and BCLKx pins must be connected: one pair
for the input serial ports and one pair for the output serial
ports. If all serial ports are in master mode and synchronous,
then only one pair of LRCLKx and BCLKx pins needs to be
connected.
Figure 27 shows a simplified view of the assignment of clock
domains to the input and output sides of the chip. Note that
each clock domain comprises two signals, namely the BCLK
(bit clock) and LRCLK (frame clock). Therefore, the 12 clock
domains contain a total of 24 clock signals.
Each clock domain is capable of acting as a master or slave. For
this reason, all LRCLK and BCLK pins are bidirectional. In slave
mode, the LRCLK and BCLK pins receive clock signals from an
external source, such as a codec. In master mode, the LRCLK
and BCLK pins output clock signals to external slave ICs.
Although a clock domain in slave mode can clock an arbitrary
number of serial ports, a clock domain in master mode can only
clock a single serial port. For Clock Domains[2:0] and Clock
Domains[11:9], the corresponding serial port is fixed as an input
or output. For assignable clock domains (Clock Domains[8:3]),
the corresponding serial port can be either an input or output,
depending on the setting of the clock pad multiplexer register
(see Table 20 for more details).
Table 20. Master Mode Clock Domain Assignment
Clock
Domain
Chip Pins
Serial Port
0
LRCLK0, BCLK0
SDATA_IN0
1
LRCLK1, BCLK1
SDATA_IN1
2
LRCLK2, BCLK2
SDATA_IN2
3
LRCLK3, BCLK3
SDATA_IN3 or SDATA_OUT31
4
LRCLK4, BCLK4
SDATA_IN4 or SDATA_OUT41
5
LRCLK5, BCLK5
SDATA_IN5 or SDATA_OUT51
6
LRCLK6, BCLK6
SDATA_IN6 or SDATA_OUT61
7
LRCLK7, BCLK7
SDATA_IN7 or SDATA_OUT71
8
LRCLK8, BCLK8
SDATA_IN8 or SDATA_OUT81
9
LRCLK9, BCLK9
SDATA_OUT0
10
LRCLK10, BCLK10
SDATA_OUT1
11
LRCLK11, BCLK11
SDATA_OUT2
1
Depends on the setting of the clock pad multiplexer register (Address 0xE240).
SERIAL
INPUT
PORTS
(×9)
SERIAL
OUTPUT
PORTS
(×9)
CLOCK DOMAINS
(×12)
0 TO 2
3 TO 8
9 TO 11
MASTER/SLAVE
SELECT
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_IN4
SDATA_IN5
SDATA_IN6
SDATA_IN7
SDATA_IN8
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
BCL
K0/
L
RCL
K0
BCL
K1/
L
RCL
K1
BCL
K2/
L
RCL
K2
BCL
K3/
L
RCL
K3
BCL
K4/
L
RCL
K4
BCL
K5/
L
RCL
K5
BCL
K6/
L
RCL
K6
BCL
K7/
L
RCL
K7
BCL
K8/
L
RCL
K8
BCL
K9/
L
RCL
K9
BCL
K10/
L
RCL
K10
BCL
K11/
L
RCL
K11
2
6
12
6
2
07696-
026
Figure 27. Simplified Serial Clock Domain Assignment
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