- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄16427 > EVAL-ADAU1442EBZ (Analog Devices Inc)BOARD EVAL FOR ADAU1442 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADAU1442EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/93頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1442 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1442 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 電路板，線纜，說(shuō)明文檔，GPIO 子板，電源 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)
ADAU1442/ADAU1445/ADAU1446
Data Sheet
Rev. D | Page 14 of 92
Pin No.
Mnemonic
Type1
Description
34
MP6
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
35
MP5
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
36
MP4
D_IO
Multipurpose, General-Purpose Input/Output. When not used, this pin can be left disconnected.
40
VDRIVE
A_OUT
Regulator Drive. Supplies the drive current for the 1.8 V regulator. The base of the voltage regulator’s
external PNP transistor is driven from VDRIVE.
41
XTALO
A_OUT
Crystal Oscillator Output. A 100 damping resistor should be connected between this pin and the
crystal. This output should not be used to directly drive a clock to another IC; the CLKOUT pin
exists for this purpose. If the crystal oscillator is not used, the XTALO pin can be left unconnected.
42
XTALI
A_IN
external master clock, this pin should be connected to the master clock signal generated by another IC.
43
PLL_FILT
A_OUT
Phase-Locked Loop Filter. Two capacitors and a resistor must be connected to this pin as shown in
44
PVDD
PWR
Phase-Locked Loop Supply. Provides the 3.3 V power supply for the PLL. This should be decoupled
to PGND with a100 nF capacitor.
45
PGND
PWR
Phase-Locked Loop Ground. Ground for the PLL supply. The AGND, DGND, and PGND pins can be
tied directly together in a common ground plane. PGND should be decoupled to PVDD with a
100 nF capacitor.
46
SPDIFI
D_IN
S/PDIF Input. Accepts digital audio data in the S/PDIF format. When not used, this pin can be left
disconnected.
47
SPDIFO
D_OUT
S/PDIF Output. Outputs digital audio data in the S/PDIF format. When not used, this pin can be left
disconnected.
48
AVDD
PWR
Analog Supply. 3.3 V analog supply for the auxiliary ADC. This pin should be decoupled to AGND
with a 100 nF capacitor.
49
AGND
PWR
Analog Ground. Ground for the analog supply. This pin should be decoupled to AVDD with a
100 nF capacitor.
53
CLKOUT
D_OUT
Master Clock Output. Used to output a master clock to other ICs in the system. Set using the
CLKMODEx pins. When not used, this pin can be left disconnected.
54
RESET
D_IN
Reset. Active-low reset input. Reset is triggered on a high-to-low edge and exited on a low-to-high
edge. For detailed information about initialization, see the Power-Up Sequence section. A reset
event sets all RAMs and registers to their default values.
55
MP3/ADC3
D_IO,
A_IN
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 3. When not used, this pin can
be left disconnected.
56
MP2/ADC2
D_IO,
A_IN
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 2. When not used, this pin can
be left disconnected.
57
MP1/ADC1
D_IO,
A_IN
Multipurpose, General-Purpose Input or Output/Auxiliary ADC Input 1. When not used, this pin can
be left disconnected.
58
MP0/ADC0
D_IO,
A_IN
Multipurpose, General-Purpose IO/Auxiliary ADC Input 0. When not used, this pin can be left
disconnected.
59
PLL1
D_IN
Phase-Locked Loop Mode Select Pin 1.
60
PLL0
D_IN
Phase-Locked Loop Mode Select Pin 0.
61
SDATA_OUT8
D_OUT
Serial Data Port 0 Output. When not used, this pin can be left disconnected.
64
BCLK11
D_IO
Bit Clock, Output Clock Domain 11. This pin is bidirectional, with the direction depending on
whether the Output Clock Domain 11 is set up as a master or slave. When not used, this pin can
be left disconnected.
65
LRCLK11
D_IO
Frame Clock, Output Clock Domain 11. This pin is bidirectional, with the direction depending on
whether the Output Clock Domain 11 is set up as a master or slave. When not used, this pin can be
left disconnected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A3AAH-4036G | IDC CABLE - ASC40H/AE40G/ASC40H |
| AMIS30622C6227RG | IC MOTOR DVR MICROSTP I2C 20SOIC |
| A1CXB-3036M | IDC CABLE- AKC30B/AE30M/X |
| VE-214-EX | CONVERTER MOD DC/DC 48V 75W |
| GCC10DRYH-S734 | CONN EDGECARD 20POS DIP .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1446EBZ | 功能描述:BOARD EVAL FOR ADAU1446 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADAU1590EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| EVAL-ADAU1592EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For ADAU1592 制造商:Analog Devices 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| EVAL-ADAU1701EB | 制造商:Analog Devices 功能描述:EVAL BOARD FOR SIGMADSP AUDIO PROCESSOR - Bulk |
| EVAL-ADAU1701EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。