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參數(shù)資料
| 型號： | EVAL-ADAU1442EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 57/93頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADAU1442 |
| 標準包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1442 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 電路板，線纜，說明文檔，GPIO 子板，電源 |
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Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 59 of 92
Every sample rate converter pair for Stereo ASRC[7:4]) can be
muted. This function is controlled by a single 12-bit register.
The mute bits (Bits[3:0]) are active high; therefore, a value of 1
mutes the corresponding ASRC, and a value of 0 unmutes the
corresponding ASRC. The muting is done with a volume ramp
and is click and pop free. If desired, the mute ramp can be
disabled (see the Stereo ASRC[7:4] Mute Ramp Disable Register
(Address 0xE143) section).
When the device is powered up and brought out of reset, the
ASRC lock bits default to a value of 0. When the master clocks
to the ASRC are enabled (see the Master Clock Enable Switch
Register (Address 0xE280) section), the corresponding ASRC
lock bits are set to 1, and the outputs are automatically muted.
When an ASRC's output rate is set (see the ASRC Output Rate
section) and it locks to a valid output clock, the corresponding
lock bit changes from 1 to 0. This signifies that the ASRC has
found the target clock rate and locked to it. From that moment
onward, the lock bit remains at 0 until the device is reset. Changing
the target rate setting or removing the output clock from the
ASRC will not cause its lock bit to change from 0 back to 1.
In the case of the ADAU1446, setting these registers does not
affect system operation in any way.
Stereo ASRC[7:4] Mute Ramp Disable Register
(Address 0xE143)
Table 40. Bit Descriptions of Register 0xE143
Bit
Position
Description
Default
[15:1]
Reserved
0
Stereo ASRC[7:4] (Channels[15:8]) mute
ramp disable
0
0 = enable ramp
1 = disable ramp
This single-bit register controls the mute behavior of Stereo
ASRC[7:4] (Channels[15:8]). When Bit 0 is set to the default (0),
Stereo ASRC[7:4] (Channels[15:8]) mute with a volume ramp.
When Bit 0 is set to 1, Stereo ASRC[7:4] mute abruptly. In
addition, setting this bit to 1 ignores the ASRC mute bits
(Bits[3:0]) in Register 0xE141 (see the Stereo ASRC[7:4] Lock
Status and Mute Register (Address 0xE141) section); therefore, a
mute only occurs on a loss of lock.
In the case of the ADAU1446, setting this register does not
affect system operation in any way.
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| EVAL-ADAU1446EBZ | 功能描述:BOARD EVAL FOR ADAU1446 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADAU1590EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| EVAL-ADAU1592EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For ADAU1592 制造商:Analog Devices 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| EVAL-ADAU1701EB | 制造商:Analog Devices 功能描述:EVAL BOARD FOR SIGMADSP AUDIO PROCESSOR - Bulk |
| EVAL-ADAU1701EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
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