- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16427 > EVAL-ADAU1442EBZ (Analog Devices Inc)BOARD EVAL FOR ADAU1442 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADAU1442EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 30/93頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADAU1442 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SigmaDSP® |
| 主要目的： | 音頻，音頻處理 |
| 嵌入式： | 是，DSP |
| 已用 IC / 零件： | ADAU1442 |
| 主要屬性： | 單芯片多通道 28/56 位音頻 DSP |
| 次要屬性： | I²C & SPI 接口 |
| 已供物品： | 電路板，線纜，說(shuō)明文檔，GPIO 子板，電源 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)當(dāng)前第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)
Data Sheet
ADAU1442/ADAU1445/ADAU1446
Rev. D | Page 35 of 92
Serial Clock Modes and Settings
Dejitter Window Register (Address 0xE221)
Table 21. Bit Descriptions of Register 0xE221
Bit
Position
Description
Default
[15:6]
Reserved
[5:0]
Dejitter window
001000
000000 = dejitter circuit bypass
000001 = minimum window
…
111111 = maximum window
Register 0xE221 is a single 6-bit register that sets the size of the
dejitter window. The dejitter circuit prevents samples from being
repeated or omitted altogether due to jitter in the frame clock
pulses coming from the serial ports in slave mode.
The dejitter window is set by default to 8 MCLK samples, which
should be suitable for most applications. However, Register 0xE221
allows this value to be tweaked in case of problems, or it allows
the dejitter circuit to be bypassed altogether by setting Bits[5:0]
to 000000.
Clock Pad Multiplexer Register (Address 0xE240)
Table 22. Bit Descriptions of Register 0xE240
Bit Position
Clock Domain1
Default
[15:6]
Reserved
5
Clock Domain 8
0
4
Clock Domain 7
0
3
Clock Domain 6
0
2
Clock Domain 5
0
1
Clock Domain 4
0
Clock Domain 3
0
1
0 = input clock domain, 1 = output clock domain.
There are six clock domains (Clock Domains[8:3]) that can be
either input or output clock domains. This is determined by a
single bit for each clock domain (see Table 22), where a setting
of 0 corresponds with an input clock domain and a setting of 1
corresponds with an output clock domain.
In Figure 28, the clock pad multiplexer is represented by six 4:2
multiplexers.
ASSIGNABLE
INPUT/OUTPUT
CLOCK DOMAINS
(×6)
3 TO 8
BCL
K3/
L
RCL
K3
BCL
K4/
L
RCL
K4
BCL
K5/
L
RCL
K5
BCL
K6/
L
RCL
K6
BCL
K7/
L
RCL
K7
BCL
K8/
L
RCL
K8
2
4:2
CLOCK PAD
MULTIPLEXERS
TO SERIAL INPUT PORTS
TO SERIAL OUTPUT PORTS
2
07696-
027
Figure 28. Clock Pad Multiplexer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A3AAH-4036G | IDC CABLE - ASC40H/AE40G/ASC40H |
| AMIS30622C6227RG | IC MOTOR DVR MICROSTP I2C 20SOIC |
| A1CXB-3036M | IDC CABLE- AKC30B/AE30M/X |
| VE-214-EX | CONVERTER MOD DC/DC 48V 75W |
| GCC10DRYH-S734 | CONN EDGECARD 20POS DIP .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADAU1446EBZ | 功能描述:BOARD EVAL FOR ADAU1446 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| EVAL-ADAU1590EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| EVAL-ADAU1592EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For ADAU1592 制造商:Analog Devices 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| EVAL-ADAU1701EB | 制造商:Analog Devices 功能描述:EVAL BOARD FOR SIGMADSP AUDIO PROCESSOR - Bulk |
| EVAL-ADAU1701EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。