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2.12 Low Power Consumption Control Circuits (CPU Intermittent Operation Function, Oscillation Stabilization Wait
Time, Clock Multiplier Function)
185
[Bit 0] Reserved bit
Always write ‘1’ to this bit.
Table 2.12.1 CG Bit Settings
(2) CKSCR (Clock select register)
s Register Configuration
s Bit Description
[Bit 15] Reserved bit
Always write ‘1’ to this bit.
[Bit 14] MCM
This bit indicates whether the main clock or PLL clock has been selected as the machine clock
source. The value ‘0’ indicates that the PLL clock is selected, and the value ‘1’ indicates that the
main clock is selected. The MCS bit is ‘0’ and the MCM bit is ‘1’ during the PLL clock oscillation
stabilization wait period. The length of the PLL clock oscillation stabilization wait period is fixed at
213 main clock cycles.
[Bits 13, 12] WS1, WS0
These bits determine the main clock oscillation stabilization wait period when wake-up from stop
mode.
The value is initialized to ‘11’ by power-on reset, and is not initialized again by any other resets.
Access is read-only.
Table 2.12.2 WS Bit Settings
[Bit 11] Reserved bit
Always write ‘1’ to this bit.
CG1
CG0
CPU clock pause cycle count
0
0 cycles (CPU clock = resource clock)
0
1
9 cycles (CPU clock: resource clock = 1: approx. 3 to 4)
1
0
17 cycles (CPU clock: resource clock = 1: approx. 5 to 6)
1
33 cycles (CPU clock: resource clock = 1: approx. 9 to 10)
WS1
WS0
Oscillation stabilization wait time
(at source oscillation of frequency 4 MHz)
0
No oscillation stabilization wait time
0
1
approx. 2.05 ms (213source oscillation counts)
1
0
approx. 8.19 ms (215 source oscillation counts)
1
approx. 65.54 ms (218 source oscillation counts)
Reserved
MCM WS1 WS0 Reserved MCS
CS1
CS0
Bit no.
Read/write
(–)
(R)
(R/W) (R/W)
(–)
(R/W) (R/W) (R/W)
Initial value
(1)
(0)
Address : 0000A1H
15
14
13
12
11
10
9
8
CKSCR