![](http://datasheet.mmic.net.cn/30000/MB90662APFM_datasheet_2367560/MB90662APFM_122.png)
2.5 UART
117
[Bit 12] CL (Character length):
This bit sets the data length of one frame.
0: 7-bit data
1: 8-bit data
[CAUTION]
7-bit data handling is available only in asynchronous (start-stop synchronized)
communications in normal mode (mode 0). In multi-processor mode (mode 1) and
CLK-synchronous communication (mode 2), 8-bit data should be used.
[Bit 11] A/D (Address/data):
This bit determines the data format of sending and receiving frames in asynchronous (start-stop
synchronized) communication in multi-processor mode (mode 1).
0: Data frame
1: Address frame
[Bit 10] REC (Receiver error clear):
This bit cleares the error flags (PE, ORE, FRE) in the SSR register.
A write value of ‘1’ is not valid, and the read value is ‘1’ at all times.
[CAUTION]
When the UART is operating in receiving-interrupt enabled status, the value ‘0’
should only be written to the REC bit if one of the error flags PE, ORE or FRE is set to
‘1.’
[Bit 9] RXE (Receiver enable):
This bit controls UART receiver operations.
0: Receiver operation prohibited
1: Receiver operation enabled
[CAUTION]
If receiver operation is prohibited while receiving is in progress (while data is present
in the receiving shift register), the receiver will not stop operating until receiving of
the current frame is completed, and the data has been stored in the receiving data
buffer SIDR register.
[Bit 8] TXE (Transmitter enable):
This bit controls UART transmitter operations.
0: Transmitter operation prohibited
1: Transmitter operation enabled
[CAUTION]
If transmitter operation is prohibited while receiving is in progress (while data is being
output from the sending register), the transmitter will not stop operating until there is
no more data remaining in the sending data buffer SODR register.