
2.13 Interrupt Controller
191
2.13.3 Detailed Register Description
(1) ICR (Interrupt control register)
s Register Configuration
[CAUTION]
Bits ICS3 to ICS0 are valid only when starting EI2OS. When starting EI2OS, set the ISE
bit to ‘1.’ When not starting EI2OS, set the ISE bit to ‘0.’ If EI2OS is not started, the ICS3-
ICS0 bits may have any value.
*The read value is ‘1.’
[CAUTION]
The ICS1 and ICS0 bits are valid for write access only, and the S1 and S0 bits are valid for
read access only.
[CAUTION]
Access by read-modify type instructions may cause abnormal operation and should not be
attempted with this register.
s Register Description
(1) Interrupt level setting bits: IL0, IL1, IL2
These bits are read/write enabled, and determine the interrupt level of the corresponding internal
resource. The initial value by reset is level 7 (no interrupt). For the relation between interrupt level
setting bits and interrupt levels, see Table 2.13.1.
ICS3 ICS2
ISE
IL2
IL1
Bit no.
Read/write
(w)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(1)
Interrupt control register
Address : ICR01 0000B1H
15
14
13
12
11
10
9
8
ICS3 ICS2
ISE
IL2
IL1
Bit no.
Read/write
(W)
(W)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
(0)
(1)
7
6
5
4
3
2
1
0
or
S1
or
S0
ICS3 ICS2
ICS1 ICS0
ISE
IL2
IL1
IL0
or
S1
or
S0
ICR03 0000B3H
ICR05 0000B5H
ICR07 0000B7H
ICR09 0000B9H
ICR11 0000BBH
ICR13 0000BDH
ICR15 0000BFH
or
S1
or
S0
ICS3 ICS2
ISE
IL2
IL1
IL0
ICS1 ICS0
or
S1
or
S0
Interrupt control register
Address : ICR00 0000B0H
ICR02 0000B2H
ICR04 0000B4H
ICR06 0000B6H
ICR08 0000B8H
ICR10 0000BAH
ICR12 0000BCH
ICR14 0000BEH
ICRxx