
3.3 Interrupts
205
(4) Miscellaneous
As a special case, hardware interrupt requests are not accepted while writing to the I/O area. This is
done in order to prevent the CPU from operating incorrectly as a result of an interrupt request occurring
while a resource interrupt control register is being overwritten.
The F2MC-16L CPU supports multiple interrupts. Therefore, while interrupt processing is being
executed, if an interrupt is generated that has a stronger interrupt level than the level of the interrupt that
is being executed, then once the current instruction being executed is completed, control shifts to the
interrupt with the higher interrupt level. Once that interrupt is completed, processing of the original
interrupt is resumed. If, while an interrupt is being processed, an interrupt is generated with the same or
a lower interrupt level, the new interrupt is put on hold and processing of the current interrupt
continues, as long as the contents of the ILM bits or the I flag are not changed by an instruction. Note
that the extended intelligent I/O service can not be started up more than once at one time; as long as one
extended intelligent I/O service process is in progress, all other interrupt requests and extended
intelligent I/O service requests are made pending.
The order of the registers saved into the stack is shown in Fig. 3.3.3.
Fig. 3.3.3 Registers Saved into the Stack
Saving of registers during an interrupt
Word (16 bits)
← SSP (value of SSP before generation of interrupt)
← SSP (value of SSP after generation of interrupt)
PCB
AH
AL
DPR
DPB
ADB
PC
PS
MSB
LSB
H
L
↑
↓