2.5 UART
119
[Bit 13] FRE (Framing error):
This interrupt request flag is set when a framing error occurs during receiving.
Once set, this flag is cleared by writing ‘0’ to the REC bit (bit 10) in the SCR register.
When this bit is set, data in the SIDR register is invalid.
0: No framing error
1: Framing error occurred
[Bit 12] RDRF (Receiver data register full):
This interrupt request flag is set to indicate that data is present in the SIDR register.
This flag is set when receiving data is loaded into the SIDR register, and is automatically cleared
when the data is read from the SIDR register.
0: No receive data
1: Receive data present
[Bit 11] TDRE (Transmitter data register empty):
This interrupt request flag is set to indicate that outgoing data has been written to the SODR register.
This flag is cleared when outgoing data is written to the SODR register. It is then reset when the
written data starts loading into the sending shifter to indicate that the next data can be written to the
SODR register.
0: Prohibits writing of transmit data
1: Enables writing of transmit data
[Bit 10] :Empty
[Bit 9] RIE (Receiver interrupt enable):
This bit controlls receiver interrupts.
0: Interrupt prohibited
1: Interrupt enabled
[CAUTION]
Receiver interrupt sources include PE, ORE and FRE errors, as well as normal
receiving as indicated by the RDRF flag.
[Bit 8] TIE (Transmitter interrupt enable):
This bit controls transmitter interrupts.
0: Interrupt prohibited
1: Interrupt enabled
[CAUTION]
Transmitter interrupt sources include tranmission requests as indicated by the TDRE
flag.