2.4 Multi-Function Timer
105
b) Use of the Dummy Transfer to Skip an Interrupt Routine
It is possible to mask interrupt sources arising from timer zero-detect events, by setting the IME bit
in the ZICR register to ‘1.’ The same procedure can be applied when EI2OS is used.
EI2OS is used to perform a designated number of data transfer cycles before executing an interrupt
routine.
This feature can be used as a control, by setting up cycles that transfer meaningless data (dummy
transfers), to delay the execution of the interrupt routine until the interrupt source has occurred five
times.
The following example illustrates the execution of the interrupt routine after 10 timer zero-detect
events.
(1) EI2OS is enabled, and descriptor settings are made in the interrupt control register (ICR).
Example: ICR04 0 8 H
descriptor address 000100H
(2) EI2OS status register (ISCS) settings are entered, including byte transfer, no buffer address
pointer increment, I/O
memory transfer.
Example: 0103H C 0 H
(3) A given address for dummy read cycles is set up for the I/O register address pointer (IOA).
Example: 0104H 0 0 0 0 H (PDR0)
(4) The desired number of transfer cycles is entered in the data counter (DCT).
Example: 0106H 0 A H
(5) An unused address is set up for the buffer address pointer for dummy write cycles.
Note that the external area should not be defined here. (Access cycle is made longer.)
With the above settings, the process operates as follows.
Fig. 2.4.19 Use of the Dummy Transfer to Skip an Interrupt Routine
This type of procedure somewhat reduces CPU processing capability, but enables the execution
of an interrupt processing routine 1 out of 10 times with no burden on the user program.
User program
EI2OS (dummy transfer)
Interrupt routine
Zero-
RETI
detect 1
Zero-
detect 2
Zero-
detect 3
Zero-
detect 10