
2.4 Multi-Function Timer
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Chapter 2: Hardware
(9) Interrupts
The following five types of interrupt requests are sent to the CPU from the various timers in the
MB90660A series chip.
Interrupt sources include timer clearing from trigger signal input, as well as zero-detect,
overflow/compare-clear match, and output-compare match events.
a. Trigger Input Interrupts
The valid edge of a signal from an external trigger input pin, setting the CES1,0 bits in the
TMCR register will set the TCIR bit in the TCSR register. At this point if the TCIE bit is set to
‘1,’ the timer will output an interrupt request to the CPU.
This interrupt can use extended intelligent I/O services.
b. Zero-detect Interrupts
When the timer value reaches 0000H, the TZIR bit in the TCSR register is set. At this point if the
TZIE bit is set to ‘1,’ the timer will output an interrupt request to the CPU.
This interrupt can be masked for a given number of occurrences.
This interrupt can use extended intelligent I/O services.
c. Timer Overflow/Compare-Clear Match Interrupts
When the timer overflows, or the compare-clear match occurs, the TMIR bit in the TCSR
register is set. At this point if the TMIE bit is set to ‘1,’ the timer will output an interrupt request
to the CPU.
This interrupt can use extended intelligent I/O services.
d. Compare-Match Interrupts
When a compare-match event occurs, the CIR bit for the corresponding compare channel is set in
the CICR register. At this point if the CIE bit corresponding to that compare channel is set to ‘1,’
the timer will output an interrupt request to the CPU.