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3.2 Resets
198
Chapter 3:Operation
3.2.3 Reset Sources
There are four reset sources, as shown in Table 3.2.1. Depending on the reset source, the initialized state
of the machine clock and watchdog function vary.
The reset source register can be used to determine the reset source.
Table 3.2.1 Reset Sources
* Reset input during stop mode requires an oscillation stabilization wait interval, regardless of the
reset source.
* Oscillation stabilization wait time at a power-on reset is fixed at 218 cycles at the source oscillation.
All other oscillation stabilization wait times are determined by the CS1/CS0 bits in the clock
selection register.
As shown in Fig. 3.2.2, there is a flip-flop corresponding to each reset source. Because the contents of
these flip-flops can be obtained by reading the watchdog timer control register, whenever it is necessary to
identify the reset generation source after the reset was released, process the value read from the watchdog
timer control register and branch to an appropriate program. For reference purposes, the watchdog timer
control register is shown again in Fig. 3.2.3.
Fig. 3.2.2 Reset Source Bit Block Diagram
Reset
Generating source
Machine clock
Watchdog timer
Oscillation
stabilization
wait?
Power on
When power is applied
Main clock
Stopped
Yes
Watchdog timer
Watchdog timer overflow
Main clock
Stopped
Yes
External pin
Low level input to RSTX pin
Previous state
retained
Previous state
retained
No
Software
Writing “0” to RST bit in
LPMCR
Previous state
retained
Previous state
retained
No
Power supply on
Power-on generation
RSTX pin
External reset request
No regular clearing
Watchdog timer reset
RST bit set
LPMCR.RST bit write
WTC register
WTC register read
F2MC-16 internal bus
detection circuit
generation detection circuit
detection circuit
RSTX=L
S
R
F / F
S
R
F / F
S
R
F / F
S
R
F / F
Delay circuit
Q