3.3 Interrupts
209
(2) Structure
The facilities related to the EI2OS can be grouped into four parts:
On-chip resources: ........ Interrupt enable bit and interrupt request bit: Control of interrupt
requests from resources
Interrupt controller: ....... ICR: Interrupt level assignment, determination of priority of
simultaneously requested interrupts, and selection of EI2OS operation
CPU: .............................. I, ILM: Comparison of level of requested interrupt with current level,
identification of interrupt enable state
Microcode: EI2OS processing steps
RAM: ............................ Descriptor: Description of EI2OS transfer information
Each of the registers are described below.
s Interrupt control registers (ICR)
The interrupt control registers are located within the interrupt controller; one exists for each I/O that has
an interrupt function. These registers have the following three functions:
Setting of the interrupt level for the corresponding peripheral
Selection of whether to handle interrupts from the corresponding peripheral as normal interrupts
or as extended intelligent I/O service interrupt
Selection of the extended intelligent I/O service channel
Note that accessing this register through a read-modify-write instruction can cause misoperation. Fig.
3.3.6 shows the bit configuration for an interrupt control register.
Note:
ICS3 to ICS0 are valid only when EI2OS is started up. When starting up EI2OS, set ISE to “1”;
when not starting it up, set ISE to “0”. If EI2OS is not to be started up, it does not matter what
ICS3 to ICS0 are set to.
* When these bits are read, a “1” is returned.
ICS1 and 0 are write-only, S1 and S0 are read-only.
Fig. 3.3.6 Interrupt Control Register (ICR)
ICS3 ICS2
ICS1 ICS0
ISE
IL2
IL1
IL0
Interrupt control register
W
*
R/W
R/W R/W
15/7 14/6
13/5
12/4
11/3
10/2
9/1
8/0
or
S1
or
S0
When reset: 00000111B