
2.5 UART
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Chapter 2: Hardware
(4) CLK Synchronous Mode
a) Transfer Data Format
The UART handles only data in NRZ (non-return to zero) format. Figure 2.5.3 shows the relation
between the sending and receiving clock and data in CLK synchronous mode.
Fig. 2.5.3 Transfer Data Format (Mode 2)
When an internal clock signal source (proprietary baud rate gemerator or internal timer) is selected,
a data receiving synchronous clock signal is automatically generated each time data is transmitted.
When an external clock source is selected it is necessary to provide an accurate 1-byte clock signal
whenever data is present in the sending data buffer register SODR (indicated by the TDRE flag =
‘0’). Note also that the sitnal must return to mark level before and after sending.
Data length is 8 bits only, and no parity bit may be attached. Also, there is no start/stop bit so that no
error detection is enabled except for overrun errors.
b) Initialization
When using CLK synchronous mode, the initial values of each of the control registers are as
follows.
(1) SMR Register
MD1, MD0
: 10
CS2, CS1, CS0
: Indicate clock input
SCKE
: 1 for proprietary baud rage generator or internal timer, 0 for external
clock
SOE
: 1 to send, 0 to receive only
(2) SCR Register
PEN
: 0
P, SBL, A/D
: These bits have no significance
CL
: 1
REC
: 0 (to initialize)
RXE, TXE
: At least one must be ‘1’
(3) SSR Register
RIE
: 1 if interrupts are used, 0 if interrupts are not used
1
0
1
0
1
0
LSB
MSB...................(mode 2)
Transfer data value: 01001101B
Mark
SODR write
SCLK
RXE,TXE
SIN,SOT