
2.4 Multi-Function Timer
101
(2) Dead-time Generator Block Operation
The dead-time generator block receives input signals from real-time output pins RT1 to RT3, and when
the DTCR register DT1 bit is ‘0’ outputs the RT1 to RT3 signals unchanged to the port block.
If the DT1 bit is ‘1’ the RT1 to 3 signals and their inverse signals are used to generate a non-
overlapping signal which is output to the port block
.
Fig. 2.4.13 Dead-time Generator Block Operation
a) Non-Overlapping Signal Generator
When the DMOD bit in the DTCR register indicates an active level ‘1’ (positive polarity) signal, a
non-overlapping signal is generated using the rising edges of the RT1 to RT3 signals and their
inverse signals, by applying a delay equivalent to the non-overlapping interval setting in the
DTCMR register.
If this interval is smaller than the non-overlapping interval determined by the RT1 to RT3 pulse
width, the 8-bit counter counts the next edge delay. This therefore prevents the signal from
fluctuating.
Pin
Output signal
U
Signal with delay applied at RT1 rising edge
V
Signal with delay applied at RT2 rising edge
W
Signal with delay applied at RT3 rising edge
X
Inverted signal with delay applied at RT1 falling edge
Y
Inverted signal with delay applied at RT2 falling edge
Z
Inverted signal with delay applied at RT3 falling edge
Dead-time timer
Selector
Output
External pin RT0
(PDR6) RT0
(PDR0) RT1
(PDR1) RT2
(PDR2) RT3
PDR3
PDR4
PDR5
U
V
W
X
Y
Z
Selector
PORT66
buffer
PORT60
PORT61
PORT62
PORT63
PORT64
PORT65
DT1
External pin P60/RT1/U
External pin P61/RT2/V
External pin P62/RT3/W
External pin P63/X
External pin P64/Y
External pin P65/Z
Positive-Polarity Non-Overlapping Signal Generation
Count value
1 machine cycle
DTCMR
Time
1 machine cycle
setting value
RT1
U
X