2.9 External Interrupts
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Fig. 2.9.2 External Interrupt Operation
In the hardware interrupt processing microprogram, the CPU reads the information in the ISE bit from
the interrupt controller to verify that the particular interrupt is selected for interrupt processing, and then
branches to the interrupt processing microprogram. The interrupt processing microprogram executes
the user-defined interrupt processing program by reading interrupt vector areas, generating interrupt
acknowledge signals to the interrupt controller, and transferring to the program counter the jump
destination address of the macro instruction generated by the vectors.
2.9.5 Precautionary Information
(1) Recovery from Standby
When using the external interrupt for the recovery from the standby in the clock stop mode, make the
input request the high-level request. Low-level request may cause anomaly. Edge request will not allow
the recovery from the standby in the clock stop mode.
(2) External Interrupt Operating Procedure
External interrupt register settings should be made using the following procedure.
1. Disable the target bits in the enable register.
2. Set the target bits in the request level setting register.
3. Clear the target bits in the source register.
4. Enable the target bits in the enable register.
(Note that steps 3 and 4 may be done in simultaneous write operations, using word access.)
When making settings to registers within this resource, it is first necessary to make a ‘disable’ setting in
the enable register. Also, it is necessary to clear the source register before returning the enable register
to ‘enable’ status. This is in order to avoid setting erroneous interrupt sources when making register
settings or enabling interrupt status.