2.7 PWM
150
Chapter 2: Hardware
2.7.4 Operating Description
The PWM block has two 8-bit reload registers for L-level and H-level settings (PRLL, PRLH). Values
written to these registers are reloaded at every alternation between L/H levels of the 8-bit down-counter
(PCNT) so that the PWM pin output value is inverted at every reload cycle caused by a counter borrow
event. This operation creates a pulse at the PWM output pin having L-level and H-level values
corresponding to these reload register values.
Operation is started, or restarted, by writing bit values to these registers.
The following table shows the relation between reload operation and pulse output.
Table 2.7.1 Relation between Reload Operation and Pulse Output
When bit 4 (PIE) in the PWMC register is ‘1,’ an interrupt request is generated, indicating a borrow event
as the counter value changes from 00H to FFH.
(1) Operating Mode
The PWM block starts operation when ‘1’ is written to bit 0 (PEN) in the PWMC (PWM mode control)
register. This starts the counter operation.
Once operation is started, the count can be stopped by writing ‘0’ to bit 0 (PEN) in the PWMC (PWM
mode control) register. After the count stops the pulse output is held at L level.
The PWM block has the following operating modes.
While the PWM is operating, a continuous pulse waveform is output with a designated frequency and
designated duty ratio (the ratio between the H-level interval and L-level interval in the pulse wave). The
PWM starts the pulse wave output, and does not stop until a ‘stop’ setting is entered.
Fig. 2.7.2 PWM Operating Mode: Output Waveform
Reload operation
Change in pin signal output
PRLH
PCNT
PWM [0
1]
Rise
PRLL
PCNT
PWM [1
0]
Fall
Output pin PWM
Operation started by PEN bit (from L-level)
(Start)
L: PRLL value
H: PRLH value
T: count clock (from PWMC clock select)
PEN
T × (L+1) s
T × (H+1) s