
2.5 UART
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Chapter 2: Hardware
(3) SIDR (Serial Input Data Register)
SODR (Serial Output Data Register)
These registers function as receiving and sending data buffer registers.
When using 7-bit data length, the must significant (D7) contains invalid data. Be sure the TDRE bit in
the SSR register is set to ‘1’ before writing to the SODR register.
Note 1:
Writing to these addresses refers to writing to the SODR register, and reading refers to reading
from the SIDR register.
Note 2:
Access by read-modify type instructions may cause abnormal operation and should not be
attempted with this register.
(4) SSR (Serial Status Register)
This register is composed of flags that indicate the operating status of the UART.
[Bit 15] PE (Parity error)
This interrupt request flag is set when a parity error occurs during receiving.
Once set, this flag is cleared by writing ‘0’ to the REC bit (bit 10) in the SCR register.
When this bit is set, data in the SIDR register is invalid.
0: No parity error
1: Parity error occurred
[Bit 14] ORE (Overrun error)
This interrupt request flag is set when an overrun error occurs during receiving.
Once set, this flag is cleared by writing ‘0’ to the REC bit (bit 10) in the SCR register.
When this bit is set, data in the SIDR register is invalid.
0: No overrun error
1: Overrun error occurred
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
R
SIDR
7
6
5
4
3
2
1
0
Indeterminate
Address : 000026H
R
Initial value
W
SODR
7
6
5
4
3
2
1
0
Indeterminate
Address : 000026H
W
D7
D6
D5
D4
D3
D2
D1
D0
PE
ORE
FRE RDRF TDRE
–
RIE
TIE
Initial value
R
R/W
SSR
15
14
13
12
11
10
9
8
00001 – 00B
Address : 000027H
R