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您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄25633 > MQ80C52CXXX-36SBR (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 PDF資料下載

型號(hào)：	MQ80C52CXXX-36SBR
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	103/1447頁(yè)
文件大?。?/td>	3788K
代理商：	MQ80C52CXXX-36SBR

6437E–ATARM–23-Apr-13

Set the START bit in the TDES Control register TDES_CR to begin the encryption or the

decryption process.

When the processing completes, the bit DATRDY in the TDES Interrupt Status Register

(TDES_ISR) raises. If an interrupt has been enabled by setting the bit DATRDY in

TDES_IER, the interrupt line of the TDES is activated.

When the software reads one of the Output Data Registers (TDES_ODATAxR), the DATRDY

bit is automatically cleared.

The Auto Mode is similar to Manual Mode, except that, as soon as the correct number of Input

Data registers is written, processing is automatically started without any action in the control

The Peripheral Data Controller (PDC) can be used in association with the TDES to perform an

encryption/decryption of a buffer without any action by the software during processing.

In this starting mode, the type of the data transfer (byte, half-word or word) depends on the oper-

ation mode as per Table 45-2.

The sequence is as follows:

Write the 64-bit key(s) in the different Key Word Registers (TDES_KEYxWxR), depending on

whether one, two or three keys are required.

Write the initialization vector (or counter) in the Initialization Vector Registers (TDES_IVxR).

The Initialization Vector Registers concern all modes except ECB.

Set the Transmit Pointer Register (TDES_TPR) to the address where the data buffer to

encrypt/decrypt is stored and the Receive Pointer Register (TDES_RPR) where it must be

encrypted/decrypted.

Transmit and receive buffers can be identical.

Set the Transmit and the Receive Counter Registers (TDES_TCR and TDES_RCR) to the

same value. This value must be a multiple of the data transfer type size (see Table 45-2).

The same requirements are necessary for the Next Pointer(s) and Counter(s) of the PDC

(TDES_TNPR, TDES_RNPR, TDES_TNCR, TDES_RNCR).

If not already done, set the bit ENDRX (or RXBUFF if the next pointers and counters are

used) in the TDES Interrupt Enable register (TDES_IER), depending on whether an interrupt

is required or not at the end of processing.

Table 45-2.

Data Transfer Type for Different Operation Modes

Operation Mode

Data Transfer Type (PDC)

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