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型號(hào)：	MQ80C52CXXX-36SBR
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	376/1447頁(yè)
文件大小：	3788K
代理商：	MQ80C52CXXX-36SBR

6437E–ATARM–23-Apr-13

Vertical to Horizontal Delay (VHDLY): The delay between the falling edge of LCDVSYNC and

the generation of LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register.

The delay is equal to (VHDLY+1) LCDDOTCK cycles.

Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of

LCDTIM2 register. The width is equal to (HPW + 1) LCDDOTCK cycles.

Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first

LCDDOTCK rising edge with valid data at the LCD Interface is configurable in the HBP field

of the LCDTIM2 register. The delay is equal to (HBP+1) LCDDOTCK cycles.

Horizontal Front Porch (HFP): The delay between end of valid data and the generation of the

next LCDHSYNC is configurable in the HFP field of the LCDTIM2 register. The delay is equal

to (HFP+VHDLY+2) LCDDOTCK cycles.

There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by

the initial latency of the datapath. The total delay in LCDC clock cycles must be higher than or

equal to the latency column in Table 49-4 on page 1328. This limitation is given by the following

VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers

PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles

DPATH_LATENCY is the datapath latency of the configuration, given in Table 49-4 on page

The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line

pointer to start over at the top of the display. The timing of this signal depends on the type of

LCD: STN or TFT LCD.

In STN mode, the high phase corresponds to the complete first line of the frame. In STN mode,

this signal is synchronized with the first active LCDDOTCK rising edge in a line.

In TFT mode, the high phase of this signal starts at the beginning of the first line. The following

timing parameters can be selected:

Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the

LCDTIM1 register. The pulse width is equal to (VPW+1) lines.

Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in

VBP field of LCDTIM1 register. The number of inactive lines is equal to VBP. This field should

be programmed with 0 in STN Mode.

Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP

field of LCDTIM2 register. The number of inactive lines is equal to VFP. This field should be

programmed with 0 in STN mode.

There are two other parameters to configure in this module, the HOZVAL and the LINEVAL

fields of the LCDFRMCFG:

HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of

active cycles in each line is equal to (HOZVAL+1) cycles. The minimum value of this

parameter is 1.

() PCLK_PERIOD

DPATH_LATENCY

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