839
6437E–ATARM–23-Apr-13
SAM9M11
there are 16 repetitions of the contents of specific address 1 register immediately following
the synchronization
An ARP request event is detected if all of the following are true:
ARP request events are enabled through bit 17 of the Wake-on-LAN register
broadcasts are allowed by bit 5 in the network configuration register
the frame has a broadcast destination address (bytes 1 to 6)
the frame has a type ID field of 0x0806 (bytes 13 and 14)
the frame has an ARP operation field of 0x0001 (bytes 21 and 22)
the least significant 16 bits of the frame’s ARP target protocol address (bytes 41 and 42)
match the value programmed in bits[15:0] of the Wake-on-LAN register
The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame.
The reserved value of 0x0000 for the Wake-on-LAN target address value does not cause an
ARP request event, even if matched by the frame.
A specific address 1 filter match event occurs if all of the following are true:
specific address 1 events are enabled through bit 18 of the Wake-on-LAN register
the frame’s destination address matches the value programmed in the specific address 1
registers
A multicast filter match event occurs if all of the following are true:
multicast hash events are enabled through bit 19 of the Wake-on-LAN register
multicast hash filtering is enabled through bit 6 of the network configuration register
the frame’s destination address matches against the multicast hash filter
the frame’s destination address is not a broadcast
38.4.13
PHY Maintenance
The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO
interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are config-
ured for the same speed and duplex configuration.
The PHY maintenance register is implemented as a shift register. Writing to the register starts a
shift operation which is signalled as complete when bit two is set in the network status register
(about 2000 MCK cycles later when bit ten is set to zero, and bit eleven is set to one in the net-
work configuration register). An interrupt is generated as this bit is set. During this time, the MSB
of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each
MDC cycle. This causes transmission of a PHY management frame on MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of
management operation, the bits have shifted back to their original locations. For a read opera-
tion, the data bits are updated with data read from the PHY. It is important to write the correct
values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read
clause 45 PHYs, bits[31:28] should be written as 0x0011. For a description of MDC generation,