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6437E–ATARM–23-Apr-13
SAM9M11
38. Ethernet MAC 10/100 (EMAC)
38.1
Description
The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 stan-
dard using an address checker, statistics and control registers, receive and transmit blocks, and
a DMA interface.
The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash regis-
ter for matching multicast and unicast addresses. It can recognize the broadcast address of all
ones, copy all frames, and act on an external address match signal.
The statistics register block contains registers for counting various types of event associated
with transmit and receive operations. These registers, along with the status words stored in the
receive buffer list, enable software to generate network management statistics compatible with
IEEE 802.3.
38.2
Embedded Characteristics
Compatibility with IEEE Standard 802.3
10 and 100 MBits per second data throughput capability
Full- and half-duplex operations
MII or RMII interface to the physical layer
Register Interface to address, data, status and control registers
DMA Interface, operating as a master on the Memory Controller
Interrupt generation to signal receive and transmit completion
128-byte transmit and 128-byte receive FIFOs
Automatic pad and CRC generation on transmitted frames
Address checking logic to recognize four 48-bit addresses
Supports promiscuous mode where all valid frames are copied to memory
Supports physical layer management through MDIO interface
Supports Wake-on-LAN. The receiver supports Wake-on-LAN by detecting the following
events on incoming receive frames:
– Magic packet
– ARP request to the device IP address
– Specific address 1 filter match
– Multicast hash filter match