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型號(hào)：	MQ80C52CXXX-36SBR
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	367/1447頁(yè)
文件大?。?/td>	3788K
代理商：	MQ80C52CXXX-36SBR

6437E–ATARM–23-Apr-13

These parameters are different for the different configurations of the LCD Controller and are

The FIFO block buffers the input data read by the DMA module. It contains two input FIFOs to

be used in Dual Scan configuration that are configured as a single FIFO when used in single

scan configuration.

The size of the FIFOs allows a wide range of architectures to be supported.

The upper threshold of the FIFOs can be configured in the FIFOTH field of the LCDFIFO regis-

ter. The LCDC core will request a DMA transfer when the number of words in each FIFO is less

than FIFOTH words. To avoid overwriting in the FIFO and to maximize the FIFO utilization, the

FIFOTH should be programmed with:

FIFOTH (in Words) = 512 - (2 x DMA_BURST_LENGTH + 3)

512 is the effective size of the FIFO in Words. It is the total FIFO memory size in single scan

mode and half that size in dual scan mode.

DMA_burst_length is the burst length of the transfers made by the DMA in Words.

This block serializes the data read from memory. It reads words from the FIFO and outputs pix-

els (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the

PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both big-

endian and little-endian formats are supported. They are configured in the MEMOR field of the

LCDCON2 register.

The organization of the pixel data in the memory depends on the configuration and is shown in

For a color depth of 24 bits per pixel there are two different formats supported: packed and

unpacked. The packed format needs less memory but has some limitations when working in 2D

Table 49-4.

Datapath Parameters

Configuration

initial_latency

cycles_per_data

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