1113
6437E–ATARM–23-Apr-13
SAM9M11
Set the Transmit Pointer Register (SHA_TPR) to the address where the data buffer to
process is stored.
Set the Transmit Counter Registers (SHA_TCR) to the same value. This value must be a
multiple of words.
Note:
The same requirements are necessary for the Next Pointer(s) and Counter(s) of the PDC
(SHA_TNPR, SHA_TNCR).
If not already done, set the bit ENDTX (or TXBUFF if the next pointers and counters are
used) in the SHA Interrupt Enable Register (SHA_IER), depending on whether an interrupt is
required or not at the end of processing.
If not already done, set the bit DATRDY in SHA Interrupt Enable Register (SHA_IER).
Enable the PDC in transmission to start the processing (SHA_PTCR).
When the processing completes, the bit ENDTX (or TXBUFF) in the SHA Interrupt Status
Register (SHA_ISR) raises. If an interrupt has been enabled by setting the corresponding in
SHA_IER, the interrupt line of the SHA is activated.
As soon as bit ENDTX (or TXBUFF) or interrupt is triggered, the DATRDY bit or interrupt line
must be triggered.
The message digest can be read from the Output Data Registers (SHA_ODATAxR read only
registers).
46.4.4
Security Features
When an unspecified register access occurs, the URAD bit in the Interrupt Status Register
(SHA_ISR) raises. Its source is then reported in the Unspecified Register Access Type field
(URAT). Only the last unspecified register access is available through the URAT field.
Several kinds of unspecified register accesses can occur:
Input Data Register written during the data processing in PDC mode
Output Data Register read during the data processing
Mode Register written during the data processing
Write-only register read access
The URAD bit and the URAT field can only be reset by the SWRST bit in the SHA_CR control
register.