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6437E–ATARM–23-Apr-13
SAM9M11
Figure 22-21. Automatic Update During AUTO-REFRESH Command and SDRAM Access
22.4.4.2
Power-down Mode
This mode is activated by setting the low-power command bits [LPCB] to ‘10’.
Power-down mode is used when no access to the SDRAM device is possible. In this mode,
power consumption is greater than in self refresh mode. This state is similar to normal mode (No
low-power mode/No self refresh mode), but the CKE pin is low and the input and output buffers
are deactivated as soon the SDRAM device is no longer accessible. In contrast to self refresh
mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64
ms). As no auto-refresh operations are performed in this mode, the DDRSDRC carries out the
refresh operation. In order to exit low-power mode, a NOP command is required in the case of
Low-power SDR-SDRAM and SDR-SDRAM devices. In the case of Low-power DDR-SDRAM
devices, the controller generates a NOP command during a delay of at least TXP. In addition,
Low-power DDR-SDRAM and DDR2-SDRAM must remain in power-down mode for a minimum
period of TCKE periods.
DDRSDRC returns to power-down mode as soon as the SDRAM device is not selected. It is
possible to define when power-down mode is enabled by setting the register LPR, timeout com-
mand bit.
00 = Power-down mode is enabled as soon as the SDRAM device is not selected
01 = Power-down mode is enabled 64 clock cycles after completion of the last access
10 = Power-down mode is enabled 128 clock cycles after completion of the last access
NOP
PRCHALL
MRS
ARFSH
NOP
0
Trfc
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
2
NOP
Update Extended mode
register
Trp
Pasr-Tcr-Ds
ACT
0
Tmrd