226
6437E–ATARM–23-Apr-13
SAM9M11
21.15.4
SMC MODE Register
Name:
SMC_MODE[0..5]
Addresses:
0xFFFFE80C [0], 0xFFFFE81C [1], 0xFFFFE82C [2], 0xFFFFE83C [3], 0xFFFFE84C [4],
0xFFFFE85C [5]
Access:
Read-write
READ_MODE:
1: The read operation is controlled by the NRD signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
0: The read operation is controlled by the NCS signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
WRITE_MODE
1: The write operation is controlled by the NWE signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
0: The write operation is controlled by the NCS signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of
the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be pro-
grammed for the read and write controlling signal.
Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
cycle is resumed from the point where it was stopped.
31
30
29
28
27
26
25
24
–
PS
–
PMEN
23
22
21
20
19
18
17
16
–
TDF_MODE
TDF_CYCLES
15
14
13
12
11
10
9
8
–
DBW
–
BAT
76543210
–
EXNW_MODE
–
WRITE_MODE
READ_MODE
EXNW_MODE
NWAIT Mode
0
Disabled
0
1
Reserved
1
0
Frozen Mode
1
Ready Mode