691
6437E–ATARM–23-Apr-13
SAM9M11
35. Timer Counter (TC)
35.1
Description
The Timer Counter (TC) includes three identical 16-bit Timer Counter channels.
Each channel can be independently programmed to perform a wide range of functions including
frequency measurement, event counting, interval measurement, pulse generation, delay timing
and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose
input/output signals which can be configured by the user. Each channel drives an internal inter-
rupt signal which can be programmed to generate processor interrupts.
The Timer Counter block has two global registers which act upon all three TC channels.
The Block Control Register allows the three channels to be started simultaneously with the same
instruction.
The Block Mode Register defines the external clock inputs for each channel, allowing them to be
chained.
Table 35-1 gives the assignment of the device Timer Counter clock inputs common to Timer
Counter 0 to 2.
Note:
1. When Slow Clock is selected for Master Clock (CSS=0inPMC Master CLock Register),
TIMER_CLOCK5 input is Master Clock, i.e., Slow CLock modified by PRES and MDIV fields.
35.2
Embedded Characteristics
Three 16-bit Timer Counter Channels
Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
Table 35-1.
Timer Counter Clock Assignment
Name
Definition
TIMER_CLOCK1
MCK/2
TIMER_CLOCK2
MCK/8
TIMER_CLOCK3
MCK/32
TIMER_CLOCK4
MCK/128
SLCK