943
6437E–ATARM–23-Apr-13
SAM9M11
– ERR_FLUSH: (for High Bandwidth Isochronous IN endpoints)
This bit is set when flushing unsent banks at the end of a microframe.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
NAK_OUT: NAK OUT
This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
CURRENT_BANK/CONTROL_DIR: Current Bank/Control Direction
– Current Bank: (all endpoints except Control endpoint)
These bits are set by hardware to indicate the number of the current bank.
Note: the current bank is updated each time the user:
– Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
– Clears the received OUT data bit to access the next bank.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
– Control Direction: (for Control endpoint only)
0 = a Control Write is requested by the Host.
1 = a Control Read is requested by the Host.
Note1: This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data).
Note2: This bit is updated after receiving new setup data.
BUSY_BANK_STA: Busy Bank Number
These bits are set by hardware to indicate the number of busy banks.
IN endpoint: it indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint: it indicates the number of busy banks filled by OUT transaction from the Host.
BYTE_COUNT: UDPHS Byte Count
Byte count of a received data packet.
00
Bank 0 (or single bank)
01
Bank 1
10
Bank 2
11
Invalid
00
All banks are free
01
1 busy bank
10
2 busy banks
11
3 busy banks