40
6437E–ATARM–23-Apr-13
SAM9M11
9.4.9
New ARM Instruction Set
.
Notes:
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
9.4.10
Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Branch instructions
Data processing instructions
Load and Store instructions
Load and Store multiple instructions
LDRH
Load Half Word
STRH
Store Half Word
LDRB
Load Byte
STRB
Store Byte
LDRBT
Load Register Byte with
Translation
STRBT
Store Register Byte with
Translation
LDRT
Load Register with Translation
STRT
Store Register with Translation
LDM
Load Multiple
STM
Store Multiple
SWP
Swap Word
SWPB
Swap Byte
MCR
Move To Coprocessor
MRC
Move From Coprocessor
LDC
Load To Coprocessor
STC
Store From Coprocessor
CDP
Coprocessor Data Processing
Table 9-2.
ARM Instruction Mnemonic List (Continued)
Mnemonic
Operation
Mnemonic
Operation
Table 9-3.
New ARM Instruction Mnemonic List
Mnemonic
Operation
Mnemonic
Operation
BXJ
Branch and exchange to Java
MRRC
Move double from coprocessor
Branch, Link and exchange
MCR2
Alternative move of ARM reg to
coprocessor
SMLAxy
Signed Multiply Accumulate 16 *
16 bit
MCRR
Move double to coprocessor
SMLAL
Signed Multiply Accumulate Long
CDP2
Alternative Coprocessor Data
Processing
SMLAWy
Signed Multiply Accumulate 32 *
16 bit
BKPT
Breakpoint
SMULxy
Signed Multiply 16 * 16 bit
PLD
Soft Preload, Memory prepare to
load from address
SMULWy
Signed Multiply 32 * 16 bit
STRD
Store Double
QADD
Saturated Add
STC2
Alternative Store from
Coprocessor
QDADD
Saturated Add with Double
LDRD
Load Double
QSUB
Saturated subtract
LDC2
Alternative Load to Coprocessor
QDSUB
Saturated Subtract with double
CLZ
Count Leading Zeroes