1060
6437E–ATARM–23-Apr-13
SAM9M11
43.8.12
AC97 Controller Channel B Mode Register
Name:
AC97C_CBMR
Address:
0xFFFAC03C
Access:
Read-write
TXRDY: Channel Transmit Ready Interrupt Enable
TXEMPTY: Channel Transmit Empty Interrupt Enable
UNRUN: Transmit Underrun Interrupt Enable
RXRDY: Channel Receive Ready Interrupt Enable
OVRUN: Receive Overrun Interrupt Enable
ENDTX: End of Transmission for Channel B Interrupt Enable
TXBUFE: Transmit Buffer Empty for Channel B Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
ENDRX: End of Reception for Channel B Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
RXBUFF: Receive Buffer Full for Channel B Interrupt Enable
0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt.
1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
SIZE: Channel B Data Size
SIZE Encoding
Note:
Each time slot in the data phase is 20 bit long. For example, if a 16-bit sample stream is being played to an AC 97 DAC, the first
16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC97 Controller
31
30
29
28
27
26
25
24
––––––––
23
22
21
20
19
18
17
16
–
PDCEN
CEN
–
CEM
SIZE
15
14
13
12
11
10
9
8
RXBUFF
ENDRX
–
TXBUFE
ENDTX
–
76543210
–
OVRUN
RXRDY
–
UNRUN
TXEMPTY
TXRDY
SIZE
Selected Data Size
0x0
20 bits
0x1
18 bits
0x2
16 bits
0x3
10 bits