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| 型號： | MT47H128M8HQ-187ELAT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 112/133頁 |
| 文件大?。?/td> | 9170K |
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Figure 51: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 97
Figure 52: Bank Read – Without Auto Precharge ............................................................................................. 99
Figure 53: Bank Read – with Auto Precharge .................................................................................................. 100
Figure 54: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window ................................................. 101
Figure 55: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window ..................................................... 102
Figure 56: Data Output Timing – tAC and tDQSCK ......................................................................................... 103
Figure 57: Write Burst ................................................................................................................................... 105
Figure 58: Consecutive WRITE-to-WRITE ...................................................................................................... 106
Figure 59: Nonconsecutive WRITE-to-WRITE ................................................................................................ 106
Figure 60: WRITE Interrupted by WRITE ....................................................................................................... 107
Figure 61: WRITE-to-READ ........................................................................................................................... 108
Figure 62: WRITE-to-PRECHARGE ................................................................................................................ 109
Figure 63: Bank Write – Without Auto Precharge ............................................................................................ 110
Figure 64: Bank Write – with Auto Precharge ................................................................................................. 111
Figure 65: WRITE – DM Operation ................................................................................................................ 112
Figure 66: Data Input Timing ........................................................................................................................ 113
Figure 67: Refresh Mode ............................................................................................................................... 114
Figure 68: Self Refresh .................................................................................................................................. 116
Figure 69: Power-Down ................................................................................................................................ 118
Figure 70: READ-to-Power-Down or Self Refresh Entry .................................................................................. 120
Figure 71: READ with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 120
Figure 72: WRITE-to-Power-Down or Self Refresh Entry ................................................................................ 121
Figure 73: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................. 121
Figure 74: REFRESH Command-to-Power-Down Entry ................................................................................. 122
Figure 75: ACTIVATE Command-to-Power-Down Entry ................................................................................ 122
Figure 76: PRECHARGE Command-to-Power-Down Entry ............................................................................ 123
Figure 77: LOAD MODE Command-to-Power-Down Entry ............................................................................ 123
Figure 78: Input Clock Frequency Change During Precharge Power-Down Mode ........................................... 124
Figure 79: RESET Function ........................................................................................................................... 126
Figure 80: ODT Timing for Entering and Exiting Power-Down Mode .............................................................. 128
Figure 81: Timing for MRS Command to ODT Update Delay .......................................................................... 129
Figure 82: ODT Timing for Active or Fast-Exit Power-Down Mode ................................................................. 129
Figure 83: ODT Timing for Slow-Exit or Precharge Power-Down Modes ......................................................... 130
Figure 84: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 130
Figure 85: ODT Turn-On Timing When Entering Power-Down Mode ............................................................. 131
Figure 86: ODT Turn-Off Timing When Exiting Power-Down Mode ............................................................... 132
Figure 87: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................ 133
1Gb: x4, x8, x16 DDR2 SDRAM
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT47H128M8HQ-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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