參數(shù)資料
型號: MT47H128M8HQ-187ELAT:E
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝: 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60
文件頁數(shù): 64/133頁
文件大?。?/td> 9170K
Table 11: AC Operating Specifications and Conditions (Continued)
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
-187E
-25E
-25
-3E
-3
-37E
-5E
Units Notes
Parameter
Symbol
Min
Max
Min Max Min Max Min Max Min Max Min Max Min Max
Command
and
Address
Internal READ-to-
PRECHARGE delay
tRTP
7.5
7.5
7.5
7.5
7.5
7.5
7.5
ns
CAS#-to-CAS#
delay
tCCD
2
2
2
2
2
2
2
tCK
Write recovery time
tWR
15
15
15
15
15
15
15
ns
Write AP recovery
+ precharge time
tDAL
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
ns
Internal WRITE-to-
READ delay
tWTR
7.5
7.5
7.5
7.5
7.5
7.5
10
ns
LOAD MODE cycle
time
tMRD
2
2
2
2
2
2
2
tCK
Refresh
REFRESH-
to-
ACTIVATE
or to
-REFRESH
interval
256Mb
tRFC
75
75
75
75
75
75
75
ns
512Mb
105
105
105
105
105
105
105
1Gb
127.5
127.5
127.5
127.5
127.5
127.5
127.5
2Gb
197.5
197.5
197.5
197.5
197.5
197.5
197.5
Average periodic
refresh
(commercial)
tREFI
7.8
7.8
7.8
7.8
7.8
7.8
7.8
s
Average periodic
refresh
(industrial)
tREFIIT
3.9
3.9
3.9
3.9
3.9
3.9
3.9
s
Average periodic
refresh
(automotive)
tREFIAT
3.9
3.9
3.9
3.9
3.9
3.9
3.9
s
CKE LOW to CK,
CK# uncertainty
tDELAY
MIN limit = tIS + tCK + tIH
MAX limit = n/a
ns
1Gb:
x4,
x8,
x16
DDR2
SDRAM
AC
Timing
Operating
Specifications
PDF:
09005aef821ae8bf
1GbDDR2.pdf
Rev.
S
10/09
EN
36
Micron
Technology,
Inc.
reserves
the
right
to
change
products
or
specifications
without
notice.
2004
Micron
Technology,
Inc.
All
rights
reserved.
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