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參數(shù)資料
| 型號(hào)： | MT47H128M8HQ-187ELAT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 7/133頁 |
| 文件大小： | 9170K |
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the WRITE diagrams show the nominal case, and where the two extreme cases (tDQSS
tion of a burst, assuming no other commands have been initiated, the DQ will remain
High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is ap-
plied after the last element of a completed burst. The new WRITE command should be
issued x cycles after the first WRITE command, where x equals BL/2.
Figure 58 (page 106) shows concatenated bursts of BL = 4 and how full-speed random
write accesses within a page or pages can be performed. An example of nonconsecutive
WRITEs is shown in Figure 59 (page 106). DDR2 SDRAM supports concurrent auto pre-
charge options, as shown in Table 42.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-
plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto
precharge disabled) might be interrupted and truncated only by another WRITE burst
as long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architec-
ture of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or
truncated with any command except another WRITE command, as shown in Figure 60
Data for any WRITE burst may be followed by a subsequent READ command. To follow
cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any
WRITE burst may be followed by a subsequent PRECHARGE command. tWR must be
met, as shown in Figure 62 (page 109). tWR starts at the end of the data burst, regard-
less of the data mask condition.
Table 42: WRITE Using Concurrent Auto Precharge
From Command
(Bank n)
To Command
(Bank m)
Minimum Delay
(with Concurrent Auto Precharge)
Units
WRITE with auto precharge
READ or READ with auto precharge
(CL - 1) + (BL/2) + tWTR
tCK
WRITE or WRITE with auto precharge
(BL/2)
tCK
PRECHARGE or ACTIVATE
1
tCK
1Gb: x4, x8, x16 DDR2 SDRAM
WRITE
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
104
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HQ-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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