- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224506 > MT47H128M8HQ-187ELAT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號： | MT47H128M8HQ-187ELAT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, ROHS COMPLIANT, FBGA-60 |
| 文件頁數(shù)： | 114/133頁 |
| 文件大?。?/td> | 9170K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁當(dāng)前第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁
DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LM command,
as shown in Figure 37 (page 80). These specifications are applicable when the DLL is
enabled for normal operation. DLL enable is required during power-up initialization
and upon returning to normal operation after having disabled the DLL for the purpose
of debugging or evaluation. Enabling the DLL should always be followed by resetting
the DLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is auto-
matically re-enabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur be-
fore a READ command can be issued to allow time for the internal clock to synchronize
with the external clock. Failing to wait for synchronization to occur may result in a viola-
tion of the tAC or tDQSCK parameters.
Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO RE-
FRESH command should be followed by a PRECHARGE ALL command.
Output Drive Strength
The output drive strength is defined by bit E1, as shown in Figure 37. The normal drive
strength for all outputs is specified to be SSTL_18. Programming bit E1 = 0 selects nor-
mal (full strength) drive strength for all outputs. Selecting a reduced drive strength
option (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the SSTL_18
drive strength. This option is intended for the support of lighter load and/or point-to-
point environments.
DQS# Enable/Disable
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the
differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single-
ended mode and the DQS# ball is disabled. When disabled, DQS# should be left float-
ing; however, it may be tied to ground via a
20Ω to 10kΩ resistor. This function is also
used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 =
0), then both DQS# and RDQS# will be enabled.
RDQS Enable/Disable
The RDQS ball is enabled by bit E11, as shown in Figure 37. This feature is only applica-
ble to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function and
timing to data strobe DQS during a READ. During a WRITE operation, RDQS is ignored
by the DDR2 SDRAM.
Output Enable/Disable
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 37. When ena-
bled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally. When
disabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus remov-
ing output buffer current. The output disable feature is intended to be used during IDD
characterization of read current.
1Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
81
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| MT48LC32M4A2P-7ELIT:G | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| MT55L256L18FT-12TR | 256K X 18 ZBT SRAM, 9 ns, PQFP100 |
| MT55L256L32FT-12 | 256K X 32 ZBT SRAM, 9 ns, PQFP100 |
| MT55L512V18PF-6 | 512K X 18 ZBT SRAM, 3.5 ns, PBGA165 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HQ-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HQ-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。