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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 12/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
12
Zarlink Semiconductor Inc.
1.0 Introduction
1.1 Functional Overview
The MT90520 8-Port Primary Rate Circuit Emulation AAL1 SAR (Segmentation and Reassembly) device is
intended to carry eight primary rate TDM (Time Division Multiplexed) circuits (DS1 or E1) over an ATM
(Asynchronous Transfer Mode) network using Circuit Emulation Services (CES). At its interface to the TDM
network, the MT90520 can be connected directly to a wide variety of industry-standard framers and LIUs (line
interface units), or to a 2.048 Mbps ST-BUS TDM backplane. At its interface to the ATM network, the MT90520
supports a wide selection of UTOPIA-compliant Physical layer devices, and customer-specific ASICs which meet
the UTOPIA (Level 1 or Level 2) specification.
The MT90520 provides several modes of Circuit Emulation Services in one device. The MT90520 implements CES
for DS1 and E1 rates, as standardized in the ATM Forum CES standard (af-vtoa-0078.000 Version 2). The
MT90520 supports both Unstructured and Structured circuit emulation of 8 independent TDM interfaces carrying
DS1 or E1 traffic. In Unstructured CES mode, 8 VCCs (Virtual Circuit Connections) are supported. In Structured
CES mode, flexible Nx64 kbps VCC assignment is supported, providing options ranging from a maximum of 256
VCCs carrying 64 kbps each (N = 1), to 8 VCCs carrying N = 32, to a smaller number of VCCs carrying up to N =
128. The MT90520 supports Structured CES with, or without, CAS (Channel Associated Signalling). MT90520
Management functions and statistics in accordance with the ATM Forum’s CES MIB (Management Information
Base) are supported.
On the TDM side, the MT90520 features eight primary rate TDM ports operating at 1.544 Mbps (Generic) or
2.048 Mbps (Generic or ST-BUS). The configurable TDM ports interface directly with DS1 or E1 framers for Nx64
Structured operation, as well as with DS1 or E1 LIUs in Unstructured mode for reduced delay in the segmentation
(ATM transmit) direction. The TDM interfaces are capable of operating with the line-rate bit clocks (1.544 MHz or
2.048 MHz), or with framed bus clocks at 1.544 MHz, 2.048 MHz or 4.096 MHz.
Each of the eight TDM ports contains a PLL (Phase Locked Loop), allowing independent timing of each TDM port.
Alternatively in SDT mode, the MT90520 can be operated in backplane mode with a single timing source. Each
independent PLL supports four modes of clock recovery: from SRTS time-stamps, from the cell-stream through the
Adaptive Clock Method, from the Physical layer (synchronous method), or from the TDM interface line-rate.
Although clock recovery is fully supported internally, an optional external PLL or clock source is also supported.
On the ATM interface side, the MT90520 device meets the ATM Forum standard UTOPIA Bus Level 2. The
MT90520 is capable of operating as a UTOPIA “master” (ATM-end) or “slave” (PHY-end). ATM-end operation
supports connection to a range of standard physical layer transceivers. PHY-end operation allows the MT90520 to
be used in systems where pre-existing ASICs are available as “master” and require a “slave” device for
interconnection. In PHY-end mode, the MT90520 is capable of Multi-PHY operation and has address inputs for this
purpose. The UTOPIA port can operate in 8-bit or 16-bit mode, with a clock rate up to 52 MHz.
The MT90520 features a 16-bit microprocessor interface, capable of operating in Intel or Motorola mode, that is
used to configure the device and monitor the management functions.
External memory (synchronous ZBT SRAM) is used in Structured CES operation to provide circular buffers in the
segmentation direction and to provide CDV buffering in the reassembly direction. In addition, if the application's
non-CBR data throughput (signalling or other) is low, the external memory can be used to provide a Receive Data
Cell Buffer and a Transmit Data Cell Buffer for non-CBR data cells to be read or written, for processing by the
external CPU. Unstructured CES operation requires no external memory (except where non-CBR data cell buffers
are desired).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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