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參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 172/180頁(yè) |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
172
Zarlink Semiconductor Inc.
8.2 Segmentation and Reassembly Latency
End-to-end latency, or delay, of the AAL1 segmentation and reassembly process of the MT90520 can be expressed
in a simplified manner as:
end-to-end delay =
cell payload assembly time + internal TX queuing + internal TX processing
+ physical layer and network delays
+ UTOPIA RX queuing + internal RX processing + pointer offset + CDV buffering
Some components of the latency, such as UDT cell payload assembly delay, are determined by the AAL1
standards. Some components of the latency are partially under the control of the application, such as SDT cell
payload assembly time where the number of channels can be increased to reduce cell payload assembly time.
Some components of the latency are a function of the MT90520 architecture, which has been designed to minimize
this latency. Finally, some components are externally determined, such as the physical layer and network delays,
and network Cell Delay Variation (CDV) which must be compensated for in the CDV buffering.
NOTE
: “N” is the number of TDM channels carried by a particular ATM VC.
Cell Payload Assembly delay is the amount of time the TDM interface requires to deliver enough data to fill an AAL1
cell. Note that the latency given in Table 105 is for the first bit of TDM data packed in the AAL1 cell, i.e. the bit which
sees the longest delay before cell transmission. Since reassembly latency is inverted from this segmentation
latency (first-in-first-out) this method gives correct end-to-end latency for all bits in the cell when segmentation and
re-assembly delays are summed. The cell payload asssembly delay in SDT mode is a function of “N”, the number of
TDM channels carried by the VC. The FLOOR[x] function means “the largest integer less than, or equal to, x” and
the CEIL[x] function means “the smallest integer greater than, or equal to, x”. Cell payload assembly is a static
delay in UDT mode. Cell payload assembly is a variable delay in SDT mode, due both to the variation in payload
size (46 bytes and 47 bytes) specified in the AAL1 standards, and to remainders when fitting N channels into the
cell payload.
Mode
UDT T1
Cell Payload Assembly
(
μ
sec)
243.5
TX Queuing
(
μ
sec)
min: 0
max: 62.9
min: 0
max: 62.9
min: 0
max: 125
min: 0
max: 125
TX
Processing
(
μ
sec)
2.3
Total TX / Segmentation
(
μ
sec)
min: 245.8
max: 308.7
min: 185.9
max: 248.8
min: 125 + FLOOR[46/N] X 125
max: 250 + CEIL[47/N] X 125
min: 250
max: 375
UDT E1
183.6
2.3
SDT
min: FLOOR[46/N] X 125
max: CEIL[47/N] X 125
125
125
SDT Trunking
N > 46
125
Table 105 - Segmentation Latency
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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