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參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 42/180頁 |
| 文件大小： | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
42
Zarlink Semiconductor Inc.
4.3.1 Overview
4.3.1.1 Segmentation Direction
In the UDT mode of operation, the segmentation process samples serial data received on DSTi and converts it to
an 8-bit parallel stream. Data is then written to the TDM Input Buffer on a byte-by-byte basis and is read by the
TX_SAR module in 47-byte blocks. Upon assertion of the LOSi (CSTi/LOSi pin) input signal, “all ones” data is
written to the TDM Input Buffer.
In the SDT mode of operation, serial data and CAS are sampled from the DSTi and CSTi inputs respectively, and
converted to separate 8-bit parallel streams. Data and CAS are then written to the Segmentation Circular Buffers
(one for each TDM channel), located in external memory. The data written to external memory is then read by the
TX_SAR module.
4.3.1.2 Reassembly Direction
In the UDT mode of operation, data is written to internal UDT Reassembly Circular Buffers (one per port) by the
UDT RX_SAR module. This data is read by the TDM module and written to the TDM Output Buffer. The data is then
read out of this buffer, converted to a serial stream and sent to the TDM output, DSTo.
In the SDT mode of operation, data and CAS are written by the SDT RX_SAR module to SDT Reassembly Circular
Buffers (one for each TDM channel) located in external memory. Data and CAS are then read from external
memory, converted to separate serial streams, and sent to the TDM outputs, DSTo and CSTo.
4.3.2 Functional Description
4.3.2.1 Segmentation Process
The incoming data on DSTi[p] can be sampled using the corresponding external pin STiCLK[p], C4M/C2M (for SDT
backplane mode), or, in special circumstances (e.g., UDT LOS condition), an internal clock generated by the Clock
Management Module.
STiMF[p] is defined as an input pin and is supplied by a framer. This pin is not used in UDT mode; in SDT mode, the
user may choose to use either frame pulses or multiframe pulses on STiMF.
In ST-BUS mode, data and CAS are sampled on the falling edge of the selected TDM input clock. In Generic mode,
data and CAS can be sampled either on the rising edge or the falling edge of the TDM input clock, depending upon
the user’s selected configuration.
UDT Mode
Since there is no CAS in the UDT mode of operation, the CSTi/LOSi pin is used as an input for the Loss of Signal
(LOS) line from an LIU. Loss of Signal polarity is specified by the user’s programming the TDM_LOS_POL bit in the
per-port TDM Control Register 1.
Serial data which is received on the DSTi pin need not be aligned to any framing. If a framing signal is provided (on
STiMF[p]), it will be ignored. Data is sampled using the TDM input clock STiCLK[p]. However, if a Loss of Signal is
detected, an internally generated clock can (depending on the user-configuration) be used to sample the data: upon
a Loss of Signal condition, if the TDM_LOS_CLK bit is set (in the per-port TDM Control Register 1), the internal
clock will be used to sample the data. If a Loss of Signal is detected and the TDM_LOS_CLK bit is not set, the
STiCLK input will continue to be used as the sampling clock.
If no Loss of Signal is detected, the sampled data is written to the TDM Input Buffer, where it is read by the
TX_SAR. On the other hand, upon detecting a Loss of Signal, the TDM module ignores the data input on DSTi and
writes all ones data to the TDM Input Buffer, for transfer to the TX_SAR.
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