- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359234 > MT90520 (Zarlink Semiconductor Inc.) 8-Port Primary Rate Circuit Emulation AAL1 SAR PDF資料下載
參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 131/180頁(yè) |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)當(dāng)前第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)
MT90520
Data Sheet
131
Zarlink Semiconductor Inc.
6.2.7 UTOPIA Interface Module
Address: 3200 + p*2 (Hex)
Label: TCR_Pp (where p represents the port number)
Reset Value: 07FF (Hex)
Label
Bit
Position
Type
Description
LATE_CELL_
PERIOD
10:0
R/W
Late Cell Timeout.
If a cell has not been received prior to this timeout (measured in 125
μ
s increments), an
internal flag is set, indicating a late cell arrival. This timer should generally be set to a value
equal to the cell assembly time, plus the expected CDV.
Default: 256 ms
In UDT mode, if this timeout period is passed, the LATE_CELL_STATUS bit in this per-port
register will be set. Additionally, if the CHECK_LATE_ARRIVALS bit is set in the UDT
Reassembly Control Register at 2000h, a dummy cell will also be inserted into the UDT
Reassembly Circular Buffer for the port.
LATE_CELL_ SE
11
R/W
Late Cell Status Service Enable.
When set, a ‘1’ on LATE_CELL_STATUS in this register will cause the
RX_TIMEOUT_SRV bit to be set in the Main Status Register at 0002h. As well, the per-
port status bit for the corresponding port will be set in the MIB Timeout Status Register at
3002h.
LATE_CELL_
STATUS
12
R/O/L
If set, indicates that a late cell event has occurred on this port. This bit can be cleared by
writing with ‘0’.
Note: This bit will only be set if a port is operating in UDT mode.
CUT_VC_SE
13
R/W
Cut VC Status Service Enable.
When set, a ‘1’ on CUT_VC_STATUS in this register will cause the RX_TIMEOUT_SRV
bit to be set in the Main Status Register at 0002h. As well, the per-port status bit for the
corresponding port will be set in the MIB Timeout Status Register at 3002h.
CUT_VC_
STATUS
14
R/O/L
If set, indicates that a cut VC event has occurred on this port (i.e, the CUT_VC_PERIOD
set in the MIB Timeout Configuration Register at 3000h has been passed without a cell
arrival). This bit can be cleared by writing with ‘0’.
Reserved
15
R/O
Always reads ‘0’.
Table 58 - Timeout Configuration Register (one per port)
Address: 4000 (Hex)
Label: UCR
Reset Value: 0004 (Hex)
Label
Bit
Position
Type
Description
SDT_N_UDT
0
R/W
SDT/UDT.
Selects between SDT mode (when set) and UDT mode (when cleared). To operate in
both modes simultaneously, this bit must be cleared. When operating in UDT mode, the
UDT VCI/VPI comparison is performed followed by the LUT (if necessary). In SDT mode,
the look-up is performed first (the UDT VPI/VCI comparison is skipped).
UNI_N_NNI
1
R/W
UNI/NNI.
Selects between UNI (when set) and NNI mode (when cleared). If NNI mode is enabled,
the GFC field of the cell header will be used in the UDT VPI/VCI comparison.
UTO_CLK_SEL
2
R/W
Selects between an external clock (when set) and an internal clock (when cleared). If an
internal clock is selected, UTO_IN_CLK and UTO_OUT_CLK are outputs, and the
frequency of the generated clock is equivalent to MCLK/2. If an external clock is
selected, UTO_IN_CLK and UTO_OUT_CLK are inputs.
Table 59 - UTOPIA Configuration Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。