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參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 14/180頁(yè) |
| 文件大小： | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
14
Zarlink Semiconductor Inc.
2.0 Features
2.1 Key Functionality
High-capacity AAL1 CES SAR device with 8 primary rate TDM ports operating at DS1 or E1 rates.
Supports major modes of Circuit Emulation Services (CES) for DS1 and E1 as per af-vtoa-0078.000:
Logical Nx64 Structured Service, using 2.048 Mbps TDM bus
DS1 Nx64 Basic Service
DS1 Nx64 Service with CAS
E1 Nx64 Basic Service
E1 Nx64 Service with CAS
DS1 Unstructured Service
E1 Unstructured Service
Supports AAL1 Trunking as per af-vtoa-0089.000:
Up to 128 TDM channels can be carried per VCC (up to 256 TDM channels per device).
Compliant with ITU-T Rec. I.363.1
Supports mixed DS1/E1 operation
Supports mixed UDT/SDT operation
Total clock recovery solution integrated on-chip
Supports non-CBR data cells and OAM cells destined for microprocessor with Transmit and Receive Data
Cell Buffer.
2.2 Microprocessor Interface
16-bit microprocessor port, configurable to Motorola or Intel timing
Indirect reads and writes possible to internal and external memory block.
Programmable interrupts for control and statistics
Allows access to internal registers and memory for initialization, control, and statistics
Allows access to external RAM for initialization, control, and observation
2.3 External Memory Interface
Supports common, commercially-available, no-latency flow-through and pipelined synchronous SRAM (ZBT,
NoBL, NtRAM)
Supports common SSRAM memory sizes - 128 K x 16, 256 K x16, 512 K x 16 and 1 M x 16; 128 K x 18,
256 K x 18, 512 K x 18 and 1 M x 18 (parity is optional)
2.4 TDM Interface
Flexible TDM port allows operation with a wide selection of framers, LIUs, switches and multiplexers.
Eight independently-timed, highly configurable, TDM interfaces can operate using:
bit-clock rate (Unstructured CES)
framed ST-BUS or Generic TDM bus (Structured CES - independent mode)
common TDM backplane clock using ST-BUS or Generic TDM bus (Structured CES - backplane mode).
Supports up to 256 bidirectional TDM channels.
2.5 UTOPIA Interface
UTOPIA Level 2 compliant 16-bit or 8-bit bus, capable of running at up to 52 MHz
Accepts data rate of up to 622 Mbps
Supports both “master” (ATM-end) and “slave” (PHY-end) operation
Supports multi-PHY (MPHY) mode when operating as a PHY device
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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