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參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 87/180頁(yè) |
| 文件大小： | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
87
Zarlink Semiconductor Inc.
RTS Reception for SRTS Clock Recovery
Although the actual SRTS clock recovery processing is a function of the Clock Management module of the
MT90520 device, the UDT RX_SAR and the SDT RX_SAR are responsible for the extraction of RTS nibbles from
incoming cells, for transfer to the clocking module.
In order to provide SRTS clock recovery, the UDT RX_SAR and SDT RX_SAR extract the RTSs (Residual Time
Stamps) carried in the CSI bits of received ATM cells. Each time an odd-sequence-numbered cell from a pre-
selected VC arrives, the RX_SAR extracts the CSI bit from the AAL1 header byte for the cell and stores it. When
the entire RTS nibble (4 bits) has been received, it is transmitted to the Clock Management module of the MT90520
device.
In UDT mode, there is only one VC per TDM port, so the user may select it to recover RTS timing information by
setting the
S
(SRTS Enable)
bit in the UDT
Reassembly Control Structure for the port’s VC. In SDT mode, it is
possible to have multiple VCs per TDM port; however, the user may select only a single VC as the source of clock
recovery data for a port (the port identified by the VC TDM Port field). This selection is made by setting the
S
(SRTS
Enable)
bit in the SDT
Reassembly Control Structure for the selected VC.
SRTS clock recovery within the MT90520 device is performed on a per-port basis, with a maximum of one VC per
port carrying clocking information. Because there is only one RTS Reception sub-module to handle all of the UDT
VCs (and another RTS Reception sub-module for all of the SDT VCs), variables associated with the recovery of the
individual RTS bits are stored in internal memory (in the form of fields within the Reassembly Control Structures for
the VCs).
Because RTS values are extracted from received cells, there is always the possibility of error (e.g., cells are
received out of order, so the RTS bits are also in the wrong order). As such, a protection mechanism is included in
the RTS extraction sub-module. Each time that the RX_SAR sends an RTS nibble to the port’s Clock Management
module, it also sends an extra bit. This bit indicates whether the current RTS value is valid. If the RTS value is
invalid, the PLL discards the RTS value (as well as the locally-generated RTS value used for comparison). The PLL
goes into holdover mode, in which the output clock rate is not adjusted based on the input signals. When the next
“valid” RTS value is received, the PLL resumes making adjustments to the output clock rate.
For more information, see Section 4.7.2.5, “Receive SRTS Circuit Sub-Module,” on page 101.
Note that in SDT mode, when using SRTS clock recovery, the MT90520 can have a maximum of 32 channels
per VC. Also, no support for SRTS clock recovery is provided when operating in CAS mode.
4.6.2 Timeout Circuitry
The timeout circuitry is used to perform a variety of tasks related to the inter-arrival time between two consecutive
cells on a VC.
4.6.2.1 Cut VC Monitoring
The first task performed by the timeout circuitry is related to the per-VC MIB statistic,
atmfCESCellLossStatus
.
According to the CES standard, this integer-valued status field must be set to a loss value “when cells are
continuously lost for the number of milliseconds specified by
atmfCESCellLossIntegrationPeriod
”. Within the
MT90520, rudimentary support for this statistic is provided on a per-VC basis. This functionality is supported via the
VC Arrival
(
V
) bit within each UDT/SDT Reassembly Control Structure. This bit is set by the UDT RX_SAR or the
SDT RX_SAR each time a cell arrives on a particular VC. However, the CPU can, via software, clear this bit to a
value of ‘0’. Software can then monitor the value of this bit at regular intervals. If the bit is still ‘0’ when polled, no
cells have been received on the VC since the bit was last cleared by the CPU. If the bit is still ‘0’ after a user-
configurable period of time, as defined within the user’s software, a cut-VC (cell loss) may be declared. Therefore,
the usage of this control structure bit, with software support, provides per-VC timeout monitoring as defined within
the CES specification.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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