參數資料
型號： ORSO42G5-2BM484I
廠商： Lattice Semiconductor Corporation
文件頁數： 103/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
53
Figure 39. OPC2 and OPC8 Block Diagrams
TX FIFO Block
In cell mode, the TXFIFO block contains the write state machine and FIFO memory. The FIFO is used to retime the
cell data from the FPGA interface at a rate of 156 MHz to the framer rate of 77.76 MHz.
The FIFO memory is implemented as a 64 x 34 FIFO. The FIFO receives data as 33-bit words with the start-of-cell
as the MSB of each word. Thus each cell occupies a maximum size of 23 words. For each link, the memory must
be capable of holding at least 2 cells or 46 words (one for write and one for read). To ensure extra space, this
capacity has been increased to 64 words. In addition, an extra bit has been reserved to store the link idle cell indi-
cator bit which is used for indicating the internally generated idle cells. Thus each word in a cell is 34 bits. Data are
written to the memory on the 156 MHz clock domain and read on the 77.76 MHz clock domain by the
Tx_Frame_Processor block. The OPC requires no response from the TXFIFO for writing data. The TXFIFO is guar-
anteed by design to not overow or underrun with correct clocking.
TX Frame Processor
The Tx_Frame_Processor (TFP) block is the primary data processing block in the both SONET mode and cell
mode. It organizes the cell data into a SONET frame before sending it to the SERDES. In cell mode, the 32-bit data
comes from the TX FIFO block. The three major TFP sub-blocks were described in the SONET mode section.
In cell mode, the Payload sub block is activated by the link_frm_sync in cell mode. A pulse on this signal from the
OPC indicates the start of a frame. Each frame contains 4 different types of bytes in cell mode:
TOH bytes (Auto TOH mode only)
Link Header (LH) bytes
Cell payload bytes
Pad bytes
TX
FIFO
OPC2
Block
OPC2_[A:B][1:2][39:0]
SYSCLK156[A:B][1:2]
32
77.76 MHz
TX
FIFO
32
77.76 MHz
TX
FIFO
OPC8
OPC8[159:0]
SYSCLK156 8
32
77.76 MHz
TX
FIFO
32
77.76 MHz
LINK 0
LINK 1
LINK 0
LINK 7
40
160
FPGA
LOGIC
Block
FPGA
LOGIC
(ORSO82G5
only)
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相關代理商/技術參數
參數描述
ORSO42G5-2BMN484C 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-2BMN484I 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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