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| 型號(hào)： | ORSO42G5-2BM484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 35/153頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
13
There are sub-modes that can be derived by enabling or disabling certain functions through programmable register
bits. Also, in cell mode, either the two-link alignment mode, for up to four alignment groups, or the eight-link align-
ment mode, where all eight links are combined into a single group, may be selected.
Data are processed in the transmit direction (FPGA to Backplane) as follows:
In the SERDES only mode, there is the option to bypass all of the SONET and cell functions and pass raw 32-bit
data from the FPGA into the 32:8 MUX block. In this mode, the user is responsible for providing an adequate
ones transition density in the transmitted stream for clock and data recovery at the receive end of the link.
In the SONET mode, a SONET frame is constructed around the input data and overhead bytes are inserted
where appropriate. The 32-bits of data per channel are scrambled before being converted to 8-bits by the 32:8
MUX block and serialized by the SERDES.
In the cell mode, 160 bits of data from the FPGA is sent to the Output Port Controller-8 block (for the
ORSO82G5 only, the block is also referred to as OPC8 since it services eight links) or 40 bits of data to an Out-
put Port Controller-2 block (referred to as the OPC2) which perform cell striping across the different SERDES
links. The cells are then transferred to the SONET clock domain of 77.76 MHz through a Transmit FIFO. A
SONET frame is constructed around the cell payload and overhead bytes inserted where appropriate before
being sent to the MUX block. The data are then converted to 8 bits by the 32:8 MUX block before being serialized
by the SERDES.
Data are processed in the receive direction (Backplane to FPGA) as follows:
In the SERDES only mode, there is the option to bypass all of the SONET and cell functions and pass raw 32-bit
data from the 8:32 DEMUX block into the FPGA interface.
In the SONET mode, the descrambled data are sent to an alignment FIFO that performs lane-to-lane deskew
and aligns data within an alignment group to a single clock domain and frame pulse. The SPE indicator is pro-
vided to the FPGA along with 32 bits of aligned data.There is an option to bypass the alignment FIFOs and pass
data directly from the descrambler to the FPGA. This mode is programmable and can be controlled per channel.
In the cell mode, the SONET framed data are descrambled and passed into a cell extractor which extracts cells
from the payload portion of the SONET frame. The cells are passed through a FIFO which performs lane-to-lane
deskew and a clock domain transfer from the SONET clock domain to the cell processing domain. The cells are
passed into the input port controller block (referred to as IPC8 or IPC2 depending on whether eight or two links
are serviced) which performs cell destriping before sending them to the FPGA interface. This cell processing fea-
ture makes the ORSO42G5 and ORSO82G5 ideal for interfacing devices with proprietary data formats across a
backplane.
Embedded Core Functional Blocks - Overview
Each channel contains transmit path and receive path logic as shown in Figure 2. Data are processed on a channel
by channel basis in the SERDES only and SONET modes. Channel by channel processing is also performed in the
cell mode by the Input Port Controller (IPC) and Output Port Controller (OPC) blocks. Support for loopback is also
provided but is not shown in Figure 2. The following sections will give an overview of the pseudo SONET protocol
supported by the ORSO42G5 and ORSO82G5 and a top level overview of the macrocells, which provide the SER-
DES Only, SONET and cell mode functionality.
SERializer and DESerializer (SERDES)
Each SERDES block is a block transceiver containing two or four channels for serial data transmission, with a per-
channel selectable data rate of 0.6-2.7 Gbps. Each SERDES block features high-speed CML interfaces and is
designed to operate in SONET backplane applications. The transceiver is controlled and congured via an 8-bit
slave interface on the system bus. Each channel has dedicated registers that are readable and writable. The device
also contains global registers for control of common circuitry and functions. There are two SERDES blocks, A and
B, in the embedded portion of the device. Each block supports full duplex serial links in the ORSO82G5 (Slice A
contains channels AA, AB, AC, and AD while slice B contains channels BA, BB, BC, and BD). A similar naming
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| ORSO42G5-2BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
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