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參數(shù)資料
| 型號： | ORSO42G5-2BM484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 83/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
35
Section (B1) BIP-8 Calculator
The section BIP-8 B1 byte in a given STS-N frame contains the scrambled BIP value for all scrambled bytes of the
previous frame. Except for the A1,A2 and J0 section overhead bytes, all bytes in a frame are scrambled. The Sec-
tion (B1) BIP-8 is calculated as the even parity of all bits in the current STS-48 frame. This value is compared to the
Section Overhead B1 byte of the next frame. B1 error counters are available that monitors the number of B1 errors
on a per-channel basis. A B1 parity error ag is also generated as a software alarm bit.
Descrambler
The data from the framer is descrambled using the SONET/SDH standard generator polynomial 1 + x
6 + x7. The
descrambling is performed in parallel on each 32-bit word per channel, synchronized to the frame pulse and can be
disabled through the software register bit.
RDI (Remote Defect Indicator) Monitor
The line RDI (RDI-L) is monitored through bits 2-0 of the K2 byte. Within the 32-bit descrambled data, a pattern of
“110” on bits 26-24 will indicate a RDI-L status. RDI-L must be detected in two consecutive frames before an RDI
alarm register bit is set. If fast_frame_mode is enabled, then the RDI alarm register bit will be set if RDI-L is
detected in one frame.
Receive FIFO
Clock domain transfers and multi-link de-skew are one of the most critical parts of this device. The main clock
domain transfer for the datapath is handled by the receive FIFO. For each link, there are two FIFOs. A 24 x 33 FIFO
is used in SONET mode.
The use of the FIFO is controlled by conguration bits.
Data can be sent from the descrambler directly to the FPGA bypassing the alignment FIFO. Data from each
channel will have an associated clock (RWCKxx at 77.76 MHz). Each channel will also provide a FP and SPE
indicator along with the data. Descrambling can be inhibited through the DSCR_INH_xx control bit.
Data can be sent directly from the 8:32 DEMUX block to the FPGA bypassing the alignment FIFO and SONET
framer and descrambler. Data from each channel will have an associated clock. No SPE or FP indicator is pro-
vided with the data.
Receive FIFO in SONET mode
The receive FIFO used in SONET mode will allow for an inter-link skew of about 300 ns (24 x 32 = 768 bits, 400 ps
per bit gives 307 ns). The FIFO is written at 77.76 MHz and read at 77.76 MHz. Once frame synchronization has
occurred, the write control logic will cause data to be written to the memory. The write control block is required to
insure that the word containing the rst A1 byte is written to the same location (address 0) in the FIFO. The syn-
chronization algorithm issues a sync pulse and sync error signals to the read control block based on the alignment
option chosen. This sync pulse will coordinate the reading of the FIFOs.
The read control logic synchronizes the reading of the FIFO for the streams that are to be aligned. The block begins
reading when the FIFO sync sub block signals that all of the applicable A1s with the appropriate margin have been
written to the FIFO. All of the read blocks to be synchronized begin reading at the same time and same location in
the memory (address 0). The block also takes the difference between the write and read address to indicate the rel-
ative skews between the links. If this difference exceeds a certain limit (programmable), then an alarm (alignment
overow) is provided to the register interface.
Multi-channel Alignment in SONET Mode – ORSO42G5
The alignment FIFO allows the transfer of all data to a common clock. The FIFO sync block allows the system to be
congured to allow the frame alignment of multiple slightly varying data streams. This optional alignment ensures
that matching SERDES streams will arrive at the FPGA end in perfect data sync. It is important to note that for all
aligned channels in a group, the SERDES transmitters on the other side of the high-speed link must all be transmit-
ting data at exactly the same frequency (0 ppm difference), i.e., using a common clock source.
The ORSO42G5 has a total of four channels (two per SERDES block). The incoming data of these channels can
be synchronized in several ways, or they can be independent of one other. Two channels within a SERDES can be
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ORSO42G5-2BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
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