參數(shù)資料
型號(hào)： ORSO42G5-2BM484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 125/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
73
Table 15 summarizes the conditions under which the embedded core registers, SERDES, and embedded core
logic are reset under user control. The embedded core status registers are also reset on read.
Table 15. ORSO42G5 and ORSO82G5 Embedded Core Reset Conditions
SERDES Characterization Test Mode (ORSO82G5 Only)
The SERDES characterization mode is a test mode that allows for direct control and observation of the transmit
and receive SERDES interfaces at chip ports. With these modes the SERDES logic and I/O can be tested one
channel at a time in either the receive or transmit modes. The SERDES characterization mode is available for only
one block (block B) of the ORSO82G5.
The characterization test mode is congured by setting bits in the control registers via the system bus. There are
four bits that set up the test mode. The transmit characterization test mode is entered when SCHAR_ENA=1 and
SCHAR_TXSEL=1. Entering this mode will cause chip port inputs to directly control the SERDES low-speed trans-
mit ports of one of the channels as shown in Table 16.
Table 16. SERDES Transmit Characterization Mode
The x in the table will be a single channel in SERDES quad B, selected by the SCHAR_CHAN control bits. The
decoding of SCHAR_CHAN is shown in Table 17.
Reset Signal
Data Paths
Control
and Status
Registers
TCK156[A:B]
TCK78[A:B]
TCK39[A:B]
RCK78[A:B]
RWCKxx
Notes
Power up
Reset
Power on reset
PASB_RESETN pin = 0
(Hard Reset)
Reset
External input pin
FPGA Conguration
Reset
DONE pin = 0
Partial FPGA Reconguration
(with option disable TRI_IO)
—
DONE pin = 0
Internal Signal FPGA_RESET = 1
Reset
—
FPGA_RESET is FPGA
sourced
FPGA GSRN signal = 0
Optional
—
Optional
—
GSRN is FPGA sourced.
Set GSRN_DISABLE = 1
to disable this reset
SOFT_RESET = 0, 1, 0
(System Bus register based)
Reset
—
Reset
—
write SOFT_RESET = 1
(ON) then
write SOFT_RESET = 0
(OFF)
TS_ALL Pin = 1
—
External input pin
SWRST_xx= 0,1,0
xx = [AC, AD, BA, BD] or
[AA,...,BD]
Selected
channel reset
—
Selected
channel reset
Selected
channel reset
Per channel software reset
(Not self-clearing, must be
manually set and cleared.)
GSWRST_[A:B] = 0,1,0
Selected
block reset
—
Selected
block reset
Selected
block reset
Per block software reset
(Not self-clearing, must be
manually set and cleared.)
Chip Port
SERDES Input
PSCHAR_CKIO0
TBCBx
PSCHAR_LDIO[9:0]
LDINBx[9:0]
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參數(shù)描述
ORSO42G5-2BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓:
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