參數(shù)資料
型號： ORSO42G5-2BM484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 139/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
86
Table 27. Per-Channel Status Register Descriptions – ORSO42G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
Channel Status Registers (Read Only) xx = [AC, AD, BC, BD]
30828 - AC
30838 - AD
30928 - BC
30938 - BD
[0:4]
RSVD
00
Reserved
—
[5]
CELL_ALIGN_ERR_xx
Cell Alignment Error, CELL_ALIGN_ERR = 1
indicates that the internal transmit frame pro-
cessor did not detect a start of cell indicator
when it was expecting a new cell. If the corre-
sponding alarm enable bit has been set, a 1 on
this bit will cause an alarm.
Cell
[6]
TX_URUN_ERR_xx
Transmit Underrun Error, TX_URUN_ERR = 1
indicates an underrun error in the transmit
Asynchronous FIFO. If the corresponding alarm
enable bit has been set, a 1 on this bit will cause
an alarm.
Cell
[7]
TX_ORUN_ERR_xx
Transmit Overrun Error, TX_ORUN_ERR = 1
indicates an overrun error in the transmit Asyn-
chronous FIFO. The TX FIFO is designed to not
overow since it sends backpressure signal to
the FPGA when it cannot accept more cells. If
the corresponding alarm enable bit has been
set, a 1 on this bit will cause an alarm.
Cell
30829 - AC
30839 - AD
30929 - BC
30939 - BD
[0]
RSVD
00
Reserved
—
[1]
OOF_xx
OOF_xx = 1 indicates OOF has been detected
in this link. If the corresponding alarm enable bit
has been set, a 1 on this bit will cause an alarm
Both
[2]
EX_SEQ_ERR_xx
Excessive Sequence Errors, EX_SEQ_ERR = 1
indicates that three consecutive cells containing
sequence errors have been detected in this link.
If the corresponding alarm enable bit has been
set, a 1 on this bit will cause an alarm.
Cell
[3]
SEQ_ERR_xx
Sequence Error, SEQ_ERR = 1 indicates that a
sequence error has been detected for a cell on
this link. If the corresponding alarm enable bit
has been set, a 1 on this bit will cause an alarm.
Cell
]4]
CELL_BIP_ERR_xx
Cell mode BIP Error, CELL_BIP_ERR = 1 indi-
cates that a BIP error has been detected in a
cell on the link. If the corresponding alarm
enable bit has been set, a 1 on this bit will cause
an alarm.
Cell
[5]
B1_ERR_xx
Bit Interleaved Parity Error, B1_ERR = 1 indi-
cates that a Section B1 error has been detected
on the link.If the corresponding alarm enable bit
has been set, a 1 on this bit will cause an alarm.
Both
[6]
RX_FIFO_OVRUN_xx
Receive FIFO Overrun, RX_FIFO_OVRUN_xx
= 1 indicates that the asynchronous RX FIFO
has detected an overrun condition. If the corre-
sponding alarm enable bit has been set, a 1 on
this bit will cause an alarm.
Cell
[7]
RDI_xx
Remote Defect Indication, RDI = 1 indicates that
a RDI has been detected on the link. If the cor-
responding alarm enable bit has been set, a 1
on this bit will cause an alarm
Both
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