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| 型號(hào)： | ORSO42G5-2BM484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 99/153頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
5
Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over
previous architectures.
Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in
faster routing times with predictable and efcient performance.
Supplemental Logic and Interconnect Cell (SLIC) provides eight 3-statable buffers, up to a 10-bit decoder, and
PAL-like AND-OR-Invert (AOI) in each programmable logic cell.
New 200 MHz embedded block-port RAM blocks,
2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be congured as:
– 1—512 x 18 (block-port, two read/two write) with optional built in arbitration.
– 1—256 x 36 (dual-port, one read/one write).
– 1—1K x 9 (dual-port, one read/one write).
– 2—512 x 9 (dual-port, one read/one write for each).
– 2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
– Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1Kx 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-
in system registers that act as the control and status center for the device.
Built-in testability:
– Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG).
– Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
– New temperature-sensing diode.
Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock
modication and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of
the input frequency up to 64x and division of the input frequency down to 1/64x possible.
New cycle stealing capability allows a typical 15% to 40% internal speed improvement after nal place and route.
This feature also enables compliance with many setup/hold and clock to out I/O specications and may provide
reduced ground bounce for output buses by allowing exible delays of switching output buffers.
PCI local bus compliant for FPGA I/Os.
Programmable Logic System Features
Improved PowerPC
860 and PowerPC II high-speed synchronous MicroProcessor Interface can be used for
conguration, readback, device control, and device status, as well as for a general-purpose interface to the
FPGA logic, RAMs, and embedded standard cell blocks. Glueless interface to synchronous PowerPC processors
with user-congurable address space provided.
New embedded system bus facilitates communication among the MicroProcessor Interface, conguration logic,
Embedded Block RAM, FPGA logic, and embedded standard cell blocks.
Variable size bused readback of conguration data with the built-in MicroProcessor Interface and system bus.
Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.
New clock routing structures for global and local clocking signicantly increases speed and reduces skew.
New local clock routing structures allow creation of localized clock trees.
Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ORSO42G5-2BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
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