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參數(shù)資料
| 型號(hào)： | ORSO42G5-2BM484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 121/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
7
ispLEVER Development System
The ispLEVER development system is used to process a design from a netlist to a congured FPGA. This system
is used to map a design onto the ORCA architecture, and then place and route it using ispLEVER development
system timing-driven tools. The development system also includes interfaces to, and libraries for, other popular
CAE tools for design entry, synthesis, simulation, and timing analysis.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER and third-party synthesis and sim-
ulation engines, provides all software and documentation required to design and verify an FPSC implementation.
Included in the kit are the FPSC conguration manager and/or complied Verilog simulation model, HSPICE and/or
IBIS models for I/O buffers, and complete online documentation. The kit's software couples with ispLEVER, provid-
ing a seamless FPSC design environment.
ORSO82G5/42G5 FPGA Logic Overview
The following sections provide a brief overview of the main architectural features of the ORSO82G5/42G5 FPGA
logic. For more detailed information, refer to the ORCA Series 4 FPGA Data Sheet which can be found on the Lat-
tice web site at www.latticesemi.com. The ORCA Series 4 FPGA Data Sheet provides detailed information required
for designing with the ORSO82G5/42G5 device. Topics covered in the ORCA Series 4 Data Sheet include:
FPGA Logic Architecture
FPGA Routing Resources
FPGA Clock Routing Resources
FPGA Programmable Input/Output Cells (PICs)
FPGA Embedded Block RAM (EBR)
Microprocessor Interface (MPI)
Phase-Locked Loops (PLLs)
Electrical Characteristics
FPGA Timing Characteristics
Power-up
Conguration
ORCA Series 4 FPGA Logic Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Lattice. It
includes enhancements and innovations geared toward today’s high-speed systems on a single chip. Designed
with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce
logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhance-
ments and are offered in a variety of packages and speed grades.
The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge
of FPGA and ASIC designs. Modular hardware and software technologies enable system-on-chip integration with
true plug-and-play design implementation.
The architecture consists of four basic elements: Programmable Logic Cells (PLCs), programmable I/O cells
(PIOs), Embedded Block RAMs (EBRs), and system-level features. These elements are interconnected with a rich
routing fabric of both global and local wires. An array of PLCs are surrounded by common interface blocks which
provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical
blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each
PLC contains a PFU, SLIC, local routing resources, and conguration RAM. Most of the FPGA logic is performed in
the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-2BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
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