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參數(shù)資料
| 型號： | ORSO42G5-2BM484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 2/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
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12.5% of the clock period increments. An automatic input buffer delay compensation mode is available for phase
delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences.
Embedded Block RAM
New 512 x 18 block-port RAM blocks are embedded in the FPGA core to signicantly increase the amount of mem-
ory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two
byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available,
as well as direct connection to the high-speed system bus.
Additional logic has been incorporated to allow signicant exibility for FIFO, constant multiply, and two-variable
multiply functions. The user can congure FIFO blocks with exible depths of 512K, 256K, and 1K including asyn-
chronous and synchronous modes and programmable status and error ags. Multiplier capabilities allow a multiply
of an 8-bit number with a 16-bit xed coefcient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-
bit output). On-the-y coefcient modications are available through the second read/write port.
Two 16 x 8-bit CAMs per embedded block can be implemented in single match, multiple match, and clear modes.
The EBRs can also be preloaded at device conguration time.
Conguration
The FPGAs functionality is determined by internal conguration RAM. The FPGAs internal initialization/congura-
tion circuitry loads the conguration data at powerup or under system control. The conguration data can reside
externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for
conguring FPGAs.
The RAM is loaded by using one of several conguration modes. Supporting the traditional master/slave serial,
master/slave parallel, and asynchronous peripheral modes, Series 4 also utilizes its MicroProcessor Interface and
Embedded System Bus to perform both programming and readback. Daisy chaining of multiple devices and partial
reconguration are also permitted.
Other conguration options include the initialization of the embedded-block RAM memories and FPSC memory as
well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE
1149.2) port is also available meeting In-System Programming (ISP) standards (IEEE 1532 Draft).
ORSO42G5 and ORSO82G5 Overview
The ORSO42G5 and ORSO82G5 FPSCs provide high-speed backplane transceivers combined with FPGA logic.
The ORSO42G5 and ORSO82G5 devices are based on the 1.5V OR4E04 ORCA FPGA and have a 36 x 36 array
of Programmable Logic Cells (PLCs). The embedded core, which contains the backplane transceivers, is attached
to the right side of the device and is integrated directly into the FPGA array. A top level diagram of the basic chip
conguration is shown in Figure 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ORSO42G5-2BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-2BMN484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BM484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-3BMN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORSO42G5-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
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