參數(shù)資料
型號： ORSO42G5-2BM484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 126/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
74
Table 17. Decoding of SCHAR_CHAN
The receive characterization test mode is entered when SCHAR_ENA=1 and SCHAR_TXSEL=0, In this mode,
one of the channels of SERDES outputs is observed at chip ports as shown in Table 18. The channel that is
observed is also based on the decoding of SCHAR_CHAN as shown in Table 18.
Table 18. SERDES Receive Characterization Mode
Embedded Core Block RAM
There are two independent memory slices (labeled A and B) in the embedded core. Each memory slice has a
capacity of 4K words by 36 bits. These are in addition to the block RAMs found in the FPGA portion of the
ORSO42G5 and ORSO82G5. Although the memory slices are in the embedded core part of the chip, they do not
interact with the rest of the embedded core circuits, but are standalone memories designed specically to increase
RAM capacity in the ORSO42G5 and ORSO82G5 chip. They can be used by the soft IP cores implemented in the
FPGA portion of the FPSC.
A block diagram of a memory slice is shown in Figure 48. Each memory slice is organized into two sections
(labeled SRAM A and SRAM B) and has one read port, one write port and four byte-write-enable (active-low) sig-
nals. Each byte has eight data bits and a control/parity bit. The control/parity bit responds to the same byte enable
(BYTEWN_x[x]) as it’s corresponding data. No special logic such as parity checking is performed on this bit by the
core. The read data from the memory is registered so that it works as a pipelined synchronous memory block. The
minimum timing specications are shown in Figure 49 and Figure 50. Signal names and functions are summarized
later in Table 19 and follow the general Series 4 naming conventions.
SCHAR_CHAN0
SCHAR_CHAN1
Channel
0
BA
1
0
BB
0
1
BC
1
BD
SERDES Output
Chip Port
LDOUTBx[9:0]
PSCHAR_LDIO[9:0]
RBC0Bx
PSCHAR_CKIO0
RBC1Bx
PSCHAR_CKIO1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORSO42G5-2BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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