參數(shù)資料
型號： ORSO42G5-2BM484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 148/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
94
Table 33. SERDES Per-Block Control Register Descriptions – ORSO82G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Per-Block Control Register (Read/Write) xx = [AA,...,BD]
30005 - A
30105 - B
[0]
RSVD
44
Reserved
—
[1]
GMASK_[A:B]
Global Mask. When GMASK_[A:B] = 1, the
transmit and receive alarms of all channel in
the SERDES block are prevented from gener-
ating an alarm (i.e., they are masked or dis-
abled). The GMASK_[A:B] bit overrides the
individual MASK_xx bits. GMASK_[A:B] = 1
on device reset.
Both
[2]
GSWRST_[A:B]
Software reset bit. The GSWRST_[A:B] bit
provides the same function as the hardware
reset for the transmit and receive sections of
all four channels, except that the device con-
guration settings are not affected when
GSWRST_[A:B] is asserted. This is not a self-
clearing bit. Once set, this bit must be manu-
ally set and cleared. The GSWRST_[A:B] bit
overrides the individual SWRST_xx bits.
GSWRST_[A:B] = 0 on device reset.
Both
[3]
GPWRDNT_[A:B]
Powerdown Transmit Function. When
GPWRDNT_[A:B] = 1, sections of the transmit
hardware for all four channels are powered
down. The GPWRDNT_[A:B] bit overrides the
individual PWRDNT_xx bits.
GPWRDNT_[A:B] = 0 on device reset.
Both
[4]
GPWRDNR_[A:B]
Powerdown Receive Function. When
GPWRDNR_[A:B] = 1, sections of the receive
hardware for all four channels are powered
down. The GPWRDNR_[A:B] bit overrides the
individual PWRDNR_xx bits.
GPWRDNR_[A:B] = 0 on device reset.
Both
[5:6]
RSVD
Reserved
—
[7]
GTESTEN_[A:B]
Global Test Enable Bit. When
GTESTEN_[A:B] = 1, the transmit and receive
sections of all channels in the block are place
in test mode. The TESTMODE_xx bits
(30006, 30106, etc.) must be set to specify
the desired test on a per-channel basis. The
GTESTEN_[A:B] bits override the individual
TESTEN_xx settings.
Factory
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ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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